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1 dsc-6159/2 december 2003 IDT72T51248 idt72t51258 idt72t51268 2.5v multi-queue ddr flow-control devices 40 bits wide with fixed 4 queues 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 ? 2003 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are registered trademarks of integrated device technology, inc features ? ? ? ? ? the multi-queue ddr flow-control device contains 4 queues each queue has a fixed size of: IDT72T51248 ? 8,192 x 40 or 16,384 x 20 or 32,768 x 10 idt72t51258 ? 16,384 x 40 or 32,768 x 20 or 65,536 x 10 idt72t51268 ? 32,768 x 40 or 65,536 x 20 or 131,072 x 10 ? ? ? ? ? write to and read from the same queue or different queues simultaneously via totally independent ports ? ? ? ? ? up to 200mhz operation of clocks ? ? ? ? ? double data rate, ddr is selectable, providing up to 400mbps bandwidth per data pin ? ? ? ? ? user selectable single or double data rate modes on both the write port and read port ? ? ? ? ? 100% bus utilization, read and write on every clock cycle ? ? ? ? ? global bus matching - all queues have same input bus width and same output bus width ? ? ? ? ? user selectable bus matching options: - x40in to x40out - x40in to x20out - x40in to x10out - x20in to x40out - x20in to x20out - x20in to x10out - x10in to x40out - x10in to x20out - x10in to x10out ? ? ? ? ? all i/o is lvttl/ hstl/ ehstl user selectable ? ? ? ? ? 3.3v tolerant inputs in lvttl mode functional block diagram ? ? ? ? ? erclk & eren echo outputs on read port ? ? ? ? ? write chip select wcs input for write port ? ? ? ? ? read chip select rcs input for read port ? ? ? ? ? user selectable idt standard mode (using ef and ff ) or fwft mode (using ir and or ) ? ? ? ? ? all 4 queues have dedicated flag outputs ff / ir , ef / or , paf and pae ? ? ? ? ? a composite full/ input ready flag gives status of the queue selected on the write port ? ? ? ? ? a composite empty/ output ready flag gives status of the queue selected on the read port ? ? ? ? ? programmable almost empty and almost full flags per queue ? ? ? ? ? dedicated serial port for flag programming ? ? ? ? ? a partial reset is provided for each queue ? ? ? ? ? power down pin minimizes power consumption ? ? ? ? ? 2.5v supply voltage ? ? ? ? ? available in a 324-pin plastic ball grid array (pbga) 19mm x 19mm, 1mm pitch ? ? ? ? ? jtag port provides boundary scan function and optional programming mode ? ? ? ? ? low power, high performance cmos technology ? ? ? ? ? industrial temperature range (-40 c to +85 c) q[39:0] x10,x20,x40 8,192 x 40 16,384 x40 32,768 x 40 8,192 x 40 16,384 x40 32,768 x 40 8,192 x 40 16,384 x40 32,768 x 40 8,192 x 40 16,384 x40 32,768 x 40 data in x10,x20,x40 queue 0 queue 1 queue 2 queue 3 d[39:0] data out ef 0/ or 0 pae 0 ef 1/ or 1 pae 1 ef 2/ or 2 pae 2 ef 3/ or 3 pae 3 cef / cor ren rcs rclk oe read control os[1:0] read port flag outputs 6159 drw01 ff 0/ ir 0 paf 0 ff 1/ ir 1 paf 1 ff 2/ ir 2 paf 2 ff 3/ ir 3 paf 3 write port flag outputs cff / cir wen wcs wclk write control is[1:0] multi-queue ddr flow-control device 2 2
2 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 list of contents: features ............................................................................................................................... .......................................................................................... 1 description ............................................................................................................................... ....................................................................................... 3 pin configuration ............................................................................................................................... .............................................................................. 5 pin descriptions ............................................................................................................................... ............................................................................. 6-8 device characteristics ............................................................................................................................... ...................................................................... 9 dc electrical characteristics ............................................................................................................................... ........................................................... 10 ac electrical characteristics ............................................................................................................................... ............................................................ 11 ac test conditions ............................................................................................................................... ......................................................................... 12 functional descriptions ............................................................................................................................... .............................................................. 14-22 signal descriptions ............................................................................................................................... .................................................................... 23-28 jtag timing specifications ............................................................................................................................... ........................................................ 29-33 tables: table 1 ? device configuration ................................................................................................. ................................................................................... 14 table 2 ? default programmable flag offsets ............................................................................................................................... ................................. 14 table 3 ? status flags for idt standard mode ................................................................................... .......................................................................... 16 table 4 ? status flags for fwft mode ........................................................................................... ............................................................................. 16 table 5 ? i/o voltage level configuration ...................................................................................... ............................................................................... 17 table 6 ? tskew measurement ............................................................................................................................... ................................................... 27 figures: figure 1. multi-queue ddr flow-control device block diagram .................................................................... ................................................................. 4 figure 2a. ac t est load ........................................................................................................ ........................................................................................ 12 figure 2b. lumped capacitive load, typical derating ............................................................................ ....................................................................... 12 figure 3. programmable flag offset programming methods ............................................................................................................................... ............ 15 figure 4. offset registers serial bit sequence ............................................................................................................................... ................................. 15 figure 5. bus-matching byte arrangement ........................................................................................ ........................................................................ 19-21 figure 6. echo read clock and data output relationship ......................................................................... ..................................................................... 28 figure 7. standard jt ag t iming ................................................................................................. .................................................................................. 29 figure 8. jtag architecture ............................................................................................................................... ............................................................ 30 figure 9. tap controller state diagram ......................................................................................... ................................................................................ 31 figure 10. master reset timing ................................................................................................. .................................................................................... 34 figure 11. partial reset t iming ................................................................................................ ...................................................................................... 35 figure 12. write cycle and full flag timing (idt standard mode, sdr to sdr, x40 in to x40 out) ................................. .............................................. 36 figure 13. write cycle and full flag timing in ddr mode ( idt standard mode, ddr to ddr, x40 in to x40 out) .................... ................................... 37 figure 14. write cycle and full flag timing with bus-matching and rate matching (idt standard mode, ddr to sdr, x10 in to x20 o ut) ...................... 38 figure 15. write cycle and full flag timing with rate matching (idt standard mode, sdr to ddr, x40 in to x40 out) .............. .................................... 39 figure 16. write timing in fwft mode (fwft mode, sdr to sdr, x40 in to x40 out) ................................................ ................................................. 40 figure 17. write cycle and first word latency timing in ddr mode (fwft mode, ddr to ddr, x40 in to x40 out) .................... ................................ 41 figure 18. read cycle, empty flag & first word latency (idt standard mode, sdr to sdr, x40 in to x40 out) ...................... .................................... 42 figure 19. read cycle, empty flag & first word latency in ddr mode (idt standard mode, ddr to ddr, x40 in to x40 out) .......... ......................... 43 figure 20. read cycle, empty flag & first word latency with bus-matching and rate-matching (idt standard mode, ddr to sdr, x40 in to x20 out) . 44 figure 21. read cycle and empty flag timing with bus-matching and rate-matching (idt standard mode, sdr to ddr, x10 in to x20 o ut) ................. 45 figure 22. read timing at full boundary (fwft mode, sdr to sdr, x40 in to x40 out) ............................................. ................................................ 46 figure 23. composite empty flag (idt standard mode, sdr to sdr, x40 in to x40 out) ............................................. ................................................. 47 figure 24. composite output ready flag (fwft mode, sdr to sdr, x40 in to x40 out) .............................................. ............................................... 47 figure 25. composite full flag (idt standard mode, sdr to sdr, x40 in to x40 out) .............................................. .................................................... 48 figure 26. composite input ready flag (fwft mode, sdr to sdr, x40 in to x40 out) ............................................... ................................................. 48 figure 27. queue switch at every clock cycle (idt standard mode, sdr to sdr, x40 in to x40 out) ................................ .......................................... 49 figure 28. echo read clock and read enable operation (idt standard mode, sdr to sdr, x40 in to x40 out) ........................ .................................. 50 figure 29. echo rclk and echo read enable operation (fwft mode, sdr to sdr, x40 in to x40 out) ................................. ................................... 51 figure 30. echo read clock and read enable operation (idt standard mode, ddr to ddr, x10 in to x10 out) ........................ ................................. 52 figure 31. loading of programmable flag registers (idt standard and fwft modes) ................................................ ................................................ 53 figure 32. reading of programmable flag registers (idt standard and fwft modes) ................................................ ................................................ 53 figure 34. synchronous programmable almost-empty flag timing (idt standard and fwft mode, sdr to sdr, x40 in to x40 out) ....... .................... 54 figure 33. synchronous programmable almost-full flag timing (idt standard and fwft mode, sdr to sdr, x40 in to x40 out) ........ ...................... 54 figure 35. power down operation ................................................................................................ ................................................................................ 55
3 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 description the multi-queue ddr flow-control devices are ideal for many applications where functions such as data differentiation and parallel buffering of multiple data paths are required. these applications may include communication and networking systems such as routers, packet prioritization systems, data acqui- sition systems, imaging systems and medical equipment. the IDT72T51248/72t51258/72t51568 multi-queue ddr flow-control devices are a single chip with four discrete fifo queues available. all four queues have a fixed density and based on the bus matching arrangement can take the following memory arrangement: for the IDT72T51248, four queues each queue being 8,192 x40 or 16,384 x20 or 32,768 x10. for the idt72t51258, four queues each queue being 16,384 x40 or 32,768 x20 or 65,536 x10. for the idt72t51268, four queues each queue being 32,768 x40 or 65,536 x20 or 131,072 x10. all queues within the device have a common data input bus (write port) and a common data output bus (read port). data written into the write port is directed to a respective queue via an internal de-multiplex operation, the queue being address by the user via a two bit input select bus. data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user via a two bit output select bus. data write and read operations are totally independent of each other, a queue may be selected on the write port and a different queue selected on the read port, or both ports may select the same queue simultaneously. bus matching is provided on this device, the bus width selection is 'global' which means that all four queues will have a fixed input width and a fixed output width. the write port bus width may be x10, x20 or x40 and the read port bus width may be x10, x20 or x40. when bus matching is used the device ensures the logical transfer of data throughput in a little endian manner. as is typical with most idt fifo?s, two types of data transfer are available, idt standard mode and first word fall through (fwft) mode. this affects the device operation and also the flag outputs. the device provides four dedicated flag outputs for all internal queue?s. these flags are: full/ input ready flag, empty/ output ready flag, programmable almost empty flag and program- mable almost full. the programmable flags have default values, but can also be set by the user to any point within the queue depth. these programmable flags can also be configured by the user for either synchronous or asynchro- nous operation. the device also provides composite flags. the multi-queue ddr device is capable of up to 200mhz operation on both write clock and read clock inputs, these clocks being totally independent of each other. along with this high speed of operation the device ports are selectable between single data rate, sdr mode and double data rate, ddr mode. if double data rate mode is selected data can be written into or read out of a queue on every rising and falling edge of a respective clock. for example, if the write clock is running at 200mhz and the write port is set-up for ddr mode a data input pin has a bandwidth of 400mbps, so for a 40 bit wide bus a total bandwidth of 16gbps can be achieved. the read port provides the user with a dedicated echo read enable, eren and echo read clock, erclk output. these outputs are helpful in higher speed applications. otherwise known as ?source synchronous clocking? the echo outputs provide tighter synchronization of the data transmitted from the multi- queue flow-control device and the read clock being received at the down- stream device. a master reset input is provided and all set-up and configuration pins are latched with respect to a master reset. for example, the bus width requirements are selected at master reset. a partial reset is provided for each internal queue. when a partial reset is performed on a queue, the read and write pointers of that queue only are reset to the first memory location. all other pointers remain the same. the device also has the capability of operating its i/o at either 2.5v lvttl, 1.5v hstl or 1.8v ehstl levels. a voltage reference, v ref input is provided for hstl and ehstl interfaces. the type of i/o is selected via the iosel pin. the core supply voltage of the device, v cc is always 2.5v, however the output pins have a separate supply, v ddq which can be 2.5v, 1.8v or 1.5v. the device also offers significant power savings in hstl/ehstl mode, most notably achieved by the presence of a power down input, pd . a jtag test port is provided. the multi-queue ddr device has a fully functional boundary scan feature, compliant with ieee 1149.1 standard test access port and boundary scan architecture. the jtag port can also be used to program the device set-up as described later in this document.
4 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 input demux 4 identical fifo queues 1.3mbit dual port memory x10, x20, x40 write control logic wen wcs wclk write port flag outputs d 0 - d 39 din is[1:0] wddr 2 ff 0/ ir 0 paf 0 ff 1/ ir 1 paf 1 ff 2/ ir 2 paf 2 ff 3/ ir 3 paf 3 cff / cir write pointer bus configuration iw[1:0] ow[1:0] 2 2 hstl i/o control iosel v ref oe x10, x20, x40 q out output register q 0 - q 39 6159 drw02 output mux mrs reset logic prs 0 prs 1 prs 2 prs 3 pd sclk flag offset programming swen sren fwft/si sdo jtag control (boundary scan) tck trst tms tdi tdo rclk ren read control logic read pointer rddr erclk eren read port flag outputs and control logic 2 ef 0/ or 0 pae 0 ef 1/ or 1 pae 1 ef 2/ or 2 pae 2 ef 3/ or 3 pae 3 cff / cor fsel[1:0] 2 os[1:0] rcs figure 1. multi-queue ddr flow-control device block diagram
5 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 a b c d e f g h j k l m n p r t v cc v cc gnd gnd v cc v cc v cc d39 q33 q36 ff2 paf3 os0 q35 v cc v cc v ddq v cc v cc v cc gnd v ddq v ddq v ddq v ddq d0 d1 d6 d3 d13 wclk gnd d38 v cc gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd prs0 pd v cc gnd v ddq v cc oe prs3 v ref mrs d23 v cc v cc fwft/si q9 q12 q15 12 34 56 78 910111213141516 a1 ball pad corner ow1 v cc d24 d27 d30 d33 d36 gnd v ddq gnd gnd d26 d29 d32 d35 d7 d11 d14 d16 d18 d20 d25 d22 d28 d31 d34 d37 q30 q18 dnc dnc q21 q24 q27 tdi sren sclk d12 d15 d17 d19 d21 d4 d5 fsel0 wddr d9 ow0 fsel1 v ddq iw0 gnd v cc trst iw1 tms tck gnd v cc v cc iosel v ddq gnd gnd v cc v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc d2 swen q6 d10 rddr v cc prs1 prs2 d8 6159 drw03 u v is1 gnd gnd v cc v cc q38 gnd ef3 os1 v cc gnd gnd v cc rcs pae3 v cc ff3 v cc ren 17 18 erclk dnc q37 q34 q1 q0 q2 q7 q10 q13 q32 q16 q19 q20 q23 q26 q29 tdo sdo q5 eren dnc q22 q25 q28 q31 q8 q11 q14 q17 q3 q4 dnc dnc rclk q39 v cc v cc v cc v ddq v cc gnd v cc v ddq v ddq v ddq gnd gnd v cc gnd gnd gnd gnd gnd v ddq gnd gnd gnd v cc gnd gnd gnd gnd gnd v ddq gnd gnd gnd gnd gnd gnd gnd v cc gnd gnd gnd gnd v ddq gnd gnd gnd v cc gnd gnd gnd v ddq gnd v cc v cc v ddq v cc v cc gnd v ddq v ddq v ddq gnd gnd v cc gnd gnd v cc gnd gnd v cc gnd gnd v cc gnd v ddq gnd gnd v ddq gnd gnd v ddq gnd gnd v ddq gnd v cc wen v cc wcs v cc v cc is0 pae0 ef0 pae1 ff1 pae2 paf0 ef1 cef ef2 ff0 paf1 cff paf2 pbga: 1mm pin pitch, 19mm x 19mm (bb324-1, order code: bb) top view pin configuration note: 1. dnc - do not connect.
6 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 cef / cor composite empty/ hstl-lvttl this flag will represent the exact status of the current queue being read without the user having to composite output output observe the correct queue empty flag. ready flag cff / cir composite full/ hstl-lvttl this flag will represent the exact status of the current queue being written without the user having to composite input output observe the correct queue full flag. ready flag d[39:0] data input bus lvttl these are the 40 data input pins. data is written into the device via these input pins on the rising edge din input of wclk and/or the falling edge in ddr mode provided wen is low. due to bus-matching not all inputs may be used, any unused inputs should be tied to low. ef 0/ or 0 empty flags 0/1/2/3 hstl-lvttl these are the empty flag (standard idt mode) or output ready flag (fwft mode) outputs for the ef 1/ or 1, or output ready output read port of queue 0, 1, 2 and 3 respectively. ef 2/ or 2, flags 0/1/2/3 ef 2/ or 3 erclk echo read clock hstl-lvttl this is the echo clock output for the read port. it is synchronous to the data output bus q[35:0] and output the input rclk. eren echo read enable hstl-lvttl this is the echo read enable output for the read port. output echo read enable is synchronous to the rclk input and is active when a read operation has occurred and a new word has been placed onto the data output bus. ff 0/ ir 0, full flags 0/1/2/3 hstl-lvttl these are the full flag (standard idt mode) or input ready flag (fwft mode) outputs for the write ff 1/ ir 1, or input ready output port of queue 0, 1, 2 and 3 respectively. ff 2/ ir 2, flags 0/1/2/3 ff 3/ ir 3 fsel flag select hstl-lvttl flag select default offset pins. during master reset, the fsel pins are used to select one of 4 default [1:0] input pae and paf offsets. both the pae and the paf offsets are programmed to the same value. values are: 00 = 7; 01 = 63; 10 = 127; 11 = 1023, meaning all four queues have the same offset. fwft/si first word fall hstl-lvttl during master reset, fwft=1 selects first word fall through mode, fwft=0 selects idt standard through/ serial input mode. after master reset this pin is used for the serial data input for the programming of the pae and input paf flags offset registers. iosel i/o select cmos during master reset if the iosel pin is high, then all inputs and outputs that are designated ?lvttl input or hstl? will be set to hstl format. if low then they will be set to lvttl format. all pins with a cmos format will remain unchanged. cmos format means that the pin is intended to be tied to v cc or gnd and these particular pins are not tested for v il or v ih . is[1:0] input select hstl-lvttl these inputs select one of the four queue?s to be written into on the write port. the address on the input input select pins is set-up with respect to the wclk. iw[1:0] input width cmos this pin is used during master reset to select the input word width bus size for the device. 00 = x10; input 01 = x20; 10 = x40 mrs master reset hstl-lvttl this input provides a full device reset. all configuration pins are sampled based on a master reset input operation. oe output enable hstl-lvttl this is the output enable for the read port. the data outputs will be placed into high impedance if input this pin is high. this input is asynchronous. os[1:0] output select hstl-lvttl these inputs select one of the four queue?s to be read from on the read port. the address on the input output select pins is set-up with respect to the rclk. ow[1:0] output width cmos this pin is used during master reset to select the output word width bus size for the device. 00 = x10; input 01 = x20; 10 = x40 pae 0, pae 1 programmable hstl-lvttl these are the programmable almost empty flag outputs for the read port of queue 0, 1, 2 and 3 pae 2, pae 3 almost empty output respectively. flags 0/1/2/3 pin descriptions symbol name i/o type description
7 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 paf0 , paf1 programmable hstl-lvttl these are the programmable almost full flag outputs for the write port of queue 0, 1, 2 and 3 paf2 , paf3 almost full output respectively. flags 0/1/2/3 pd power down hstl-lvttl this input provides considerable power saving in hstl/ehstl mode. if this pin is low, the input input level translators for all the data input pins, clocks and non-essential control pins are turned off. when pd is brought high, a power-up sequence timing will have to be met before the inputs will be read. it is essential that the user respects these conditions when powering down the part and powering up the part, so as to not produce runt pulses or glitches on the clocks if the clocks are free running. prs 0, prs 1 partial hstl-lvttl these are the partial reset inputs for each internal queue. resets the read and write and the flag prs 2, prs 3 reset 0/1/2/3 input pointers to zero, sets the output register to zero. during partial reset, the existing mode (idt or fwft) and the programmable flag settings are all retained. q[39:0] (2) data output bus lvttl these are the 40 data output pins. data is read out of the device via these output pins on the rising output edge of rclk provided that ren is low, oe is low and the queue is selected. due to bus-matching not all outputs may be used, any unused outputs should not be connected. rclk read clock hstl-lvttl this is the clock input for the read port. all read port operations will be synchronous to this clock input. input rcs read chip select hstl-lvttl this is the read chip select input for the read port. all read operations will occur synchronous to t he input rclk clock input provided that ren and rcs are low. when rcs is high the outputs are in high- impedance and reads are disabled. rddr read port ddr cmos during master reset, this pin selects ddr or sdr format. if rddr=1, then the rclk reads a word input on both the rising and falling edge of rclk. if rddr=0 then the rclk reads a word only on the rising edge of rclk. ren read enable hstl-lvttl this is the read enable input for the read port. all read operations will occur synchronous to the rclk input clock input provided that ren and rcs are low. sclk serial clock hstl-lvttl serial clock for programming and reading the pae and paf offset registers. on the rising edge of each input sclk, when swen is low, one bit of data is shifted into the pae and paf registers. on the rising edge of each sclk, when sren is low, one bit of data is shifted out of the readback pae and paf registers. the reading of the pae and paf registers is non-destructive. sdo serial data output hstl-lvttl when sren is brought low before the rising edge of sclk, the contents of the pae and paf output registers are copied to a readback serial register. while sren is maintained low, on each rising edge of sclk, one bit of data is shifted out of this readback register through the sdo output pin. sren serial read enable hstl-lvttl when sren is brought low before the rising edge of sclk, the contents of the pae and paf input registers are copied to a readback serial register. while sren is maintained low, on each rising edge of sclk, one bit of data is shifted out of this readback register through the sdo output pin. swen serial write enable hstl-lvttl on each rising edge of sclk when swen is low, data from the fwft/si pin is serially loaded input into the pae and paf registers. each bit loaded into the registers go directly to the pae / paf registers and the new flags will be in operation. tck (3) jtag clock hstl-lvttl clock input for jtag function. one of four terminals required by ieee standard 1149.1-1990. test input operations of the device are synchronous to tck. data from tms and tdi are sampled on the rising edge of tck and tdo change on the falling edge of tck. if the jtag function is not used this signal needs to be tied to gnd. tdi (3) jtag test data hstl-lvttl one of four terminals required by ieee standard 1149.1-1990. during the jtag boundary scan input input operation, test data is serially scanned to the tdi on the rising edge of tck to the instruction register, id register, bypass register, or boundary scan chain. an internal pull-up resistor forces tdi high if left unconnected. tdo (3) jtag test data hstl-lvttl one of four terminals required by ieee standard 1149.1-1990. during the jtag boundary scan output output operation, test data is serially loaded via the tdo on the falling edge of tck from either the instruction register, id register, bypass register and boundary scan chain. this output is high-impedance except when shifting, while in shift-dr and shift-ir controller states. pin descriptions (continued) symbol name i/o type description
8 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 tms (3) jtag mode select hstl-lvttl tms is a serial input pin. one of four terminals required by ieee standard 1149.1-1990. tms directs input the device through its tap controller states sampled on the rising edge of tck. an internal pull-up resistor forces tms high if left unconnected. trst (3) jtag reset hstl-lvttl trst is an asynchronous reset pin for the jtag controller. the jtag tap controller is automatically input reset upon power-up. if the tap controller is not properly reset then the queue outputs will always be in high-impedance. if the jtag function is used but the user does not want to use trst , then trst can be tied with mrs to ensure proper queue operation. if the jtag function is not used then this signal needs to be tied to gnd. an internal pull-up resistor forces trst high if left unconnected. wclk write clock hstl-lvttl this is the clock input for the write port. all write port operations will be synchronous to this clock input input on either the rising edge (sdr mode) or rising or falling edge (ddr mode). wcs write chip select hstl-lvttl this is the write chip select input for the write port. all write operations will occur synchronous to the input wclk clock input provided that wen and wcs are low, sampled on wclk. wddr write port ddr cmos during master reset, this pin selects ddr or sdr format. if wddr=1, then the wclk writes a word input on both the rising and falling edge. if wddr=0 then the wclk writes a word only on the rising edge. wen write enable hstl-lvttl this is the write enable input for the write port. all write operations will occur synchronous to the wclk input clock input provided that wen and wcs are low, sampled on the rising edge of wclk. v cc +2.5 supply pwr power supply for the chip core, 2.5v. v ddq output rail voltage pwr power supply for all of the chip?s outputs. 2.5v for lvttl outputs, 1.5v for hstl outputs or 1.8v for ehstl outputs. gnd ground pin gnd ground connection. v ref reference voltage analog voltage reference input for hstl inputs. pin descriptions (continued) symbol name i/o type description notes: 1. all cmos pins should remain unchanged. cmos format means that the pin is intended to be tied directly to v cc or gnd and these particular pins are not tested for v ih or v il . 2. all unused outputs should be left un-connected. 3. these pins are for the jtag port. please refer to pages 29-33, figure 7-9 for jtag information.
9 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 absolute maximum ratings notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. compliant with jedec jesd8-5. v cc terminal only. symbol parameter (1) conditions max. unit c in (2,3) input v in = 0v 10 (3) pf capacitance c out (1,2) output v out = 0v 10 pf capacitance capacitance (t a = +25 c, f = 1.0mhz) notes: 1. with output deselected, ( oe v ih ). 2. characterized values, not currently tested. 3. c in for vref is 20pf. symbol parameter min. typ. max. unit v cc supply voltage with reference to gnd 2.375 2.5 2.625 v v ddq output supply voltage ? lvttl 2.375 2.5 2.625 v ? ehstl 1.7 1.8 1.9 v ? hstl (2) 1.4 1.5 1.6 v v ref voltage reference input ? ehstl 0.8 0.9 1.0 v ? hstl (2) 0.68 0.75 0.9 v v ih input high voltage ? lvttl 1.7 ? 3.45 v ? ehstl v ref +0.1 ? v ddq +0.3 v ? hstl (2) v ref +0.1 ? v ddq +0.3 v v il input low voltage ? lvttl ? ? 0.7 v ? ehstl -0.3 ? v ref -0.1 v ? hstl (2) -0.3 ? v ref -0.1 v t a operating temperature commercial 0 ? +70 c t a operating temperature industrial -40 ? +85 c recommended dc operating conditions notes: 1. v ref is only required for hstl or ehstl inputs. v ref should be tied low for lvttl operation. 2. compliant with jedec jesd8-6. 3. gnd = ground. symbol rating com'l & ind'l unit v term terminal voltage ?0.5 to +3.6 (2) v with respect to gnd t stg storage temperature ?55 to +125 c i out dc output current ?50 to +50 ma
10 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 dc electrical characteristics (industrial: v cc = 2.5v 0.125v, t a = -40 c to +85 c) symbol parameter min. max. unit i li input leakage current ?10 +10 a i lo output leakage current ?10 +10 a v oh (7) output logic ?1? voltage, i oh = ?8 ma @lvttl v ddq -0.4 ? v i oh = ?8 ma @ehstl v ddq -0.4 ? v i oh = ?8 ma @hstl v ddq -0.4 ? v v ol output logic ?0? voltage, i ol = 8 ma @lvttl ? 0.4 v i ol = 8 ma @ehstl ? 0.4 v i ol = 8 ma @hstl ? 0.4 v i cc1 (1,2,3) active v cc current -- lvttl ? 144 ma (see note 8 for test conditions) -- ehstl ? 234 ma -- hstl ? 231 ma i cc3 (1,2,3) standby v cc current -- lvttl ? 82 ma (see note 9 for test conditions) -- ehstl ? 163 ma -- hstl ? 159 ma i cc5 (1,2,3) power down v cc current -- lvttl ? 8 ma (see note 10 for test conditions) -- ehstl ? 25 ma -- hstl ? 24 ma notes: 1. both wclk and rclk toggling at 20mhz. 2. data inputs toggling at 10mhz. 3. typical i cc1 calculation : for lvttl i/o i cc1 (ma) = 6 x fs , fs = wclk frequency = rclk frequency (in mhz) for hstl or ehstl i/o i cc1 (ma) = 90+ (6 x fs) , fs = wclk frequency = rclk frequency (in mhz) 4. typical i ddq calculation: with data outputs in high-impedance: i ddq (ma) = 0.25 x fs, fs = wclk = rclk frequency (in mhz) with data outputs in low-impedance: i ddq (ma) = (c l x v ddq x fs x n) /2000 fs = wclk frequency = rclk frequency (in mhz), v ddq = 2.5v for lvttl; 1.5v for hstl; 1.8v for ehstl t a = 25c, c l = capacitive load (pf), n = number of bits switching 5. total power consumed: pt = [(v cc x i cc ) + (v ddq x i ddq )]. i oh = -8ma for all voltage levels. 6. i oh 8ma, i ol -8ma. 7. outputs are not 3.3v tolerant. 8. v cc = 2.5v, wclk = rclk = 20mhz, wen = ren = low, wcs = rcs = low, oe = low, pd = high. 9. v cc = 2.5v, wclk = rclk = 20mhz, wen = ren = high, wcs = rcs = high, oe = low, pd = high. 10. v cc = 2.5v, wclk = rclk = 20mhz, wen = ren = high, wcs = rcs = high, oe = low, pd = low.
11 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 ac electrical characteristics (1) (commercial: v cc = 2.5v 0.15v, t a = 0 c to +70 c;industrial: v cc = 2.5v 0.15v, t a = -40 c to +85 c; jedec compliant) commercial & industrial commercial & industrial IDT72T51248l5 IDT72T51248l6-7 idt72t51258l5 idt72t51258l6-7 idt72t51268l5 idt72t51268l6-7 symbol parameter min. max. min. max. unit f s clock cycle frequency (wclk & rclk) ? 200 ? 150 mhz t a data access time 0.6 3.6 0.6 3.8 ns t clk clock cycle time 5 ? 6.7 ? ns t clkh clock high time 2.3 ? 2.8 ? ns t clkl clock low time 2.3 ? 2.8 ? ns t ds data setup time 1.5 ? 2.0 ? ns t dh data hold time 0.5 ? 0.5 ? ns t ens enable setup time 1.5 ? 2.0 ? ns t enh enable hold time 0.5 ? 0.5 ? ns f c clock cycle frequency (sclk) ? 10 ? 10 mhz t aso serial output data access time ? 20 ? 20 ns t sclk serial clock cycle 100 ? 100 ? ns t sckh serial clock high 45 ? 45 ? ns t sckl serial clock low 45 ? 45 ? ns t sds serial data in setup 15 ? 15 ? ns t sdh serial data in hold 5 ? 5 ? ns t sens serial enable setup 5 ? 5 ? ns t senh serial enable hold 5 ? 5 ? ns t rs reset pulse width 200 ? 200 ? ns t rss reset setup time 15 ? 15 ? ns t rsr reset recovery time 10 ? 10 ? ns t rsf reset to flag and output time ? 12 ? 15 ns t olz ( oe - q n) (2) output enable to output in low-impedance 0.6 3.6 0.8 3.8 ns t ohz (2) output enable to output in high-impedance 0.6 3.6 0.8 3.8 ns t oe output enable to data output valid 0.6 3.6 0.8 3.8 ns t wff write clock to ff or ir ? 3.6 ? 3.8 ns t ref read clock to ef or or ? 3.6 ? 3.8 ns t cef read clock to composite ef or or ? 3.6 ? 3.8 ns t cff write clock to composite ff or ir ? 3.6 ? 3.8 ns t pafs write clock to synchronous programmable almost-full flag ? 3.6 ? 3.8 ns t paes read clock to synchronous programmable almost-empty flag ? 3.6 ? 3.8 ns t pafa write clock to asynchronous programmable almost-full flag ? 10 ? 12 ns t paea read clock to asynchronous programmable almost-empty flag ? 10 ? 12 ns t erclk rclk to echo rclk output ? 4.0 ? 4.3 ns t clken rclk to echo ren output ? 3.6 ? 3.8 ns t d time between data switching and erclk edge 0.4 ? 0.5 ? ns t rcslz rclk to active from high-impedance ? 3.6 ? 3.8 ns t rcshz rclk to high-impedance ? 3.6 ? 3.8 ns t skew1 skew time between rclk and wclk for ef / or and ff / ir 4? 5?ns t skew2 skew time between rclk and wclk for ef / or and ff / ir in5? 7?ns ddr mode t skew3 skew time between rclk and wclk for pae and paf 5? 7?ns notes: 1. this applies to both ddr and sdr modes of operation. 2. values guaranteed by design, not currently tested.
12 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 ac test loads figure 2a. ac test load 6159 drw04 50 ? v ddq /2 i/o z 0 = 50 ? input pulse levels 0.25 to 1.25v input rise/fall times 0.4ns input timing reference levels 0.75 output reference levels v ddq /2 hstl 1.5v ac test conditions input pulse levels gnd to 2.5v input rise/fall times 1ns input timing reference levels v cc /2 output reference levels v ddq /2 lvttl 2.5v ac test conditions note: 1. v ddq = 1.5v. note: 1. for lvttl, v cc = v ddq = 2.5v. input pulse levels 0.4 to 1.4v input rise/fall times 0.4ns input timing reference levels 0.9 output reference levels v ddq /2 extended hstl 1.8v ac test conditions note: 1. v ddq = 1.8v. figure 2b. lumped capacitive load, typical derating 6159 drw04a 6 5 4 3 2 1 20 30 50 80 100 200 capacitance (pf) ? t cd (typical, ns)
13 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 output enable & disable timing v ih oe v il t oe & t olz 100mv 100mv t ohz 100mv 100mv single output normally low single output normally high v ol v oh v ddq /2 6159 drw05 output enable output disable v ddq /2 v ddq /2 v ddq /2 t olz current data in output register t oe v ddq /2 output bus v ddq /2 t ohz read chip select enable & disable timing notes: 1. ren is high. 2. oe is low. v ih rcs v il t ens t enh t rcslz rclk v ddq 2 v ddq 2 100mv 100mv t rcshz 100mv 100mv single output normally low single output normally high v ol v oh v ddq 2 v ddq 2 6158 drw06 output bus current data in output register v ddq 2 v ddq 2 notes: 1. ren is high. 2. rcs is low.
14 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 functional descriptions master reset & device configuration - mrs during master reset the device configuration and settings are determined, this includes the following: 1. idt standard or first word fall through (fwft) flag timing mode 2. single or double data rates on both the write and read ports 3. programmable flag mode, synchronous or asynchronous timing 4. write and read port bus widths, x40, x20, or x10 5. default offsets for the programmable flags, 7, 63, 127, or 1023 6. lvttl or hstl i/o selection 7. default starting queue the state of the configuration inputs during master reset will determine which of the above modes are selected. a master reset comprises of pulsing the mrs input pin from high to low for a period of time (t rs ) with the configuration inputs held in their respective states. table 1 summarizes the configuration modes available during master reset. they are described as follows: idt standard or fwft mode . the two available flag timing modes are selected using the fwft/si input. if fwft/si is low during master reset then idt standard mode is selected, if it is high then fwft mode is selected. the timing modes are described later in timing modes: idt standard vs first word fall through (fwft) mode section. single data rate (sdr) or double data rate (ddr). the input/output data rates are port selectable. this is a versatile feature that allows the user to select either sdr or ddr on the write ports and/or reads ports of all queues using the wddr and/or rddr inputs. if wddr is low during master reset then the write ports of all queues will function in sdr mode, if it is high then the write ports will be ddr mode. if rddr is low during master reset then the read ports of all queues will function in sdr mode, if it is high then the read port will be ddr mode. this feature is described in the signal descriptions section. programmable almost empty/full flags . the almost empty and almost full offsets are user programmable, with offset values listed in table 2. both pae and paf are double-buffered and updated based on the rising edge of their respective clocks. pae with respect to rclk and paf with respect to wclk. selectable bus width . the bus width can be selected on independently the read and write ports using the iw and ow inputs. iw pins set the write port width to x40, x20 or x10 bits wide. the ow pins set the read port to x40, x20 or x10 bits wide. programmable flag offset values. these offset values can be user programmed or they can be set to one of four default values during a master reset. for default programming, the state of the fsel[1:0] inputs during master reset will determine the value. table 2, default programmable offsets lists the four offset values and how to select them. for programming the offset values to a specific number, use the serial programming signals (sclk, swen , sren , fwft/si) to load the value into the offset register. you may also use the jtag port on this device to load the offset value. keep in mind that you must disable the serial programming signals if you plan to use the jtag port for loading the offset values. to disable the serial programming signals, tie sclk, swen , sren , and fwft/si to v cc . a thorough explanation of the serial and jtag programming of the flag offset values is provided in the next section titled ?serial write and reading of offset registers?. i/o level selection. the i/os can be selected for either 2.5v lvttl levels or 1.5v hstl / 1.8v ehstl levels. the state of the iosel input will determine which i/o level will be selected. if iosel is high then the applicable i/os will be 1.5v hstl or 1.8v ehstl, depending on the voltage level applied to v ddq and v ref . for hstl, v ddq = 1.5v and v ref = ? v ddq. for ehstl v ddq = 1.8v and v ref = ? v ddq . if iosel is low then the applicable i/os will be 2.5v lvttl. as noted in the pin description section, iosel is a cmos input and must be tied to either v cc or gnd for proper operation. input and output selection. during master reset, the value of is[1:0] and os[1:0] will be held constant and indicates which internal queue the read and write port will select for initial operation. data will be written to or read from this internal queue on the first valid write and read operation after master reset. IDT72T51248 / idt72t51258 / idt72t51268 fsel1 fsel0 offsets n,m 00 7 0163 1 0 127 1 1 1023 table 2 default programmable flag offsets notes: 1. in default programming, the offset value selected applies to all internal queues. 2. to prog ram different offset values for each queue, serial pr ogramming must be used. table 1 device configuration pins values configuration fwft/si 0 idt standard 1 fwft wddr 0 single data rate write port 1 double data rate write port rddr 0 single data rate read port 1 double data rate read port iw[1:0] 00 write port is 10 bits wide 01 write port is 20 bits wide 10 write port is 40 bits wide 11 restricted ow[1:0] 00 read port is 10 bits wide 01 read port is 20 bits wide 10 read port is 40 bits wide 11 restricted fsel[1:0] 00 programmable flag offset registers value = 7 01 programmable flag offset registers value = 63 10 programmable flag offset registers value = 127 11 programmable flag offset registers value = 1023 iosel 0 all applicable i/os (except cmos) are lvttl 1 all applicable i/os (except cmos) are hstl/ehstl is[1:0] 00 queue0 01 queue1 10 queue2 11 queue3 os[1:0] 00 queue0 01 queue1 10 queue2 11 queue3
15 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 6159 drw08 offset register pae 3 paf 3 pae 2 paf 2 pae 1 paf 1 pae 0 paf 0 14 - 26 27 - 39 40 - 52 53 - 65 66 - 78 1 - 13 79 - 91 92 - 104 serial bits IDT72T51248 iw/ow = x20 or idt72t51258 iw/ow = x40 IDT72T51248 iw/ow = x20 or idt72t51258 iw/ow = x20 or idt72t51268 iw/ow = x40 IDT72T51248 iw/ow = x40 idt72t51268 iw/ow = x10 idt72t51258 iw/ow = x10 or idt72t51268 iw/ow = x20 15 - 28 29 - 42 43 - 56 57 - 70 71 - 84 1 - 14 85 - 98 99 - 112 16 - 30 31 - 45 46 - 60 61 - 75 76 - 90 1 - 15 91 - 105 106 - 120 17 - 32 33 - 48 49 - 64 65 - 80 81 - 96 1 - 16 97 - 112 113 - 128 18 - 34 35 - 51 52 - 68 69 - 85 86 - 102 1 - 17 103 - 119 120 - 136 figure 4. offset registers serial bit sequence sclk tdi* 0008 tck* swen 0 sren 1 no operation iw/ow = x40 serial read from registers: 104 bits for the IDT72T51248 112 bits for the idt72t51258 120 bits for the idt72t51268 1 bit for each rising sclk edge starting with empty offset (lsb) ending with full offset (msb) IDT72T51248 idt72t51258 idt72t51268 serial write into register: 104 bits for the IDT72T51248 112 bits for the idt72t51258 120 bits for the idt72t51268 1 bit for each rising sclk edge starting with empty offset (lsb) ending with full offset (msb) 6159 drw07 iw/ow = x20 serial write into register: 112 bits for the IDT72T51248 120 bits for the idt72t51258 128 bits for the idt72t51268 1 bit for each rising sclk edge starting with empty offset (lsb) ending with full offset (msb) 0007 11 serial read from registers: 112 bits for the IDT72T51248 120 bits for the idt72t51258 128 bits for the idt72t51268 1 bit for each rising sclk edge starting with empty offset (lsb) ending with full offset (msb) no operation don?t care except 0008 & 0007 10 xx iw/ow = x10 serial write into register: 120 bits for the IDT72T51248 128 bits for the idt72t51258 136 bits for the idt72t51268 1 bit for each rising sclk edge starting with empty offset (lsb) ending with full offset (msb) serial read from registers: 120 bits for the IDT72T51248 128 bits for the idt72t51258 136 bits for the idt72t51268 1 bit for each rising sclk edge starting with empty offset (lsb) ending with full offset (msb) no operation notes: * programming done using the jtag port. 1. the programming methods apply to both idt standard mode and fwft mode. 2. parallel programming is not featured in this device. 3. the number of bits includes programming to all four dedicated pae / paf offset registers. figure 3. programmable flag offset programming methods
16 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 6159 drw09 0 1 to n (1) (n+1) to (8,192 - m) 8,192 f f p a f p a e e f hhl l hhl h hlhh llhh IDT72T51248 idt72t51258 idt72t51258 IDT72T51248 IDT72T51248 ow = x20 number of words in queue ow = x10 idt72t51268 ow = x40 idt72t51268 idt72t51258 idt72t51268 0 1 to n (1) (n+1) to (16,384 - m) 16,384 0 1 to n (1) (n+1) to (32,768 - m) 32,768 0 1 to n (1) (n+1) to (65,536 - m) 65,536 0 1 to n (1) (n+1) to (131,072 - m) 131,072 0 1 to n+1 (1) (n+2) to (8,193 - m) 8,193 f f p a f p a e e f hhl l hhl h hlhh llhh IDT72T51248 idt72t51258 idt72t51258 IDT72T51248 IDT72T51248 ow = x20 number of words in queue ow = x10 idt72t51268 ow = x40 idt72t51268 idt72t51258 idt72t51268 0 1 to n+1 (1) (n+2) to (16,385 - m) 16,385 0 1 to n+1 (1) (n+2) to (32,769 - m) 32,769 0 1 to n+1 (1) (n+2) to (65,537 - m) 65,537 0 1 to n+1 (1) (n+2) to (131,073 - m) 131,073 timing modes: idt standard vs first word fall through (fwft) mode the IDT72T51248/72t51258/72t51268 support two different timing modes of operation: idt standard mode or first word fall through (fwft) mode. the selection of which mode will operate is determined during master reset, by the state of the fwft input. during master reset, if the fwft pin is low, then idt standard mode will be selected. this mode uses the empty flag ( ef ) to indicate whether or not there are any words present in the queue. it also uses the full flag ( ff ) to indicate whether or not the queue has any free space for writing. in idt standard mode, every word read from the queue, including the first, must be requested using the read enable ( ren ) and rclk. if the fwft pin is high during master reset, then fwft mode will be selected. this mode uses output ready ( or ) to indicate whether or not there is valid data at the data outputs. it also uses input ready ( ir ) to indicate whether or not the queue has any free space for writing. in the fwft mode, the first word written to an empty queue goes directly to output bus after three rclk rising edges, applying rcs = low is not necessary. however, subsequent words must be accessed using the rcs and rclk. various signals, in both inputs and outputs operate differently depending on which timing mode is in effect. the timing mode selected affects all internal queues equally. idt standard mode in this mode, the status flags ff , paf , pae , and ef operate in the manner outlined in table 3. to write data into the queue, write enable ( wen ) and write chip select wcs must be low. data presented to the d[39:0] lines will be clocked into the queue on subsequent transitions of the write clock (wclk). after the first write is performed, the empty flag ( ef ) will go high after three clock cycles. subsequent writes will continue to fill up the queue. the programmable almost-empty flag ( pae ) will go high after n + 1 words have been loaded into the queue, where n is the empty offset value. the default setting for these values are listed in table 3. this parameter is also user programmable as described in the serial writing and reading of offset registers section. continuing to write data into the queue without performing read operations will cause the programmable almost-full flag ( paf ) to go low. again, if no reads are performed, the paf will go low after (8,192-m) writes for the IDT72T51248, (16,384-m) writes for the idt72t51258, and (32,768-m) writes for the idt72t51268. this is assuming the i/o bus width is configured to x40. if the i/o is x20, then paf will go low after (16,384-m) writes for the IDT72T51248, (32,768-m) writes for the idt72t51258, and (65,536-m) writes for the idt72t51268. if the i/o is x10, then paf will go low after (32,768-m) writes for the IDT72T51248, (65,536-m) writes for the idt72t51258, and (131,072-m) writes for the idt72t51268. the offset ?m? is the full offset value. the default setting for these values are listed in table 3. this parameter is also user programmable. see the section on serial writing and reading of offset registers for details. when the queue is full, the full flag ( ff ) will go low, inhibiting further write operations. if no reads are performed after a reset, ff will go low after d writes to the queue. if the i/o bus width is configured to x40, then d = 8,192 writes note: 1. n, m = 7 if fsel[1:0] = 00, n, m = 63 if fsel[1:0] = 01, n, m = 127 if fsel[1:0] = 10, n, m = 1023 if fsel[1:0] = 11. note: 1. n, m = 7 if fsel[1:0] = 00, n, m = 63 if fsel[1:0] = 01, n, m = 127 if fsel[1:0] = 10, n, m = 1023 if fsel[1:0] = 11. table 3 status flags for idt standard mode table 4 status flags for fwft mode
17 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 for the IDT72T51248, 16,384 writes for the idt72t51258, and 32,768 writes for the idt72t51268. if the i/o is x20, then d = 16,384 writes for the IDT72T51248, 32,768 writes for the idt72t51258, and 65,536 writes for the idt72t51268. if the i/o is x10, then d = 32,768 writes for the IDT72T51248, 65,536 writes for the idt72t51258, and 131,072 writes for the idt72t51268. if the queue is full, the first read operation will cause ff to go high after two clock cycles. subsequent read operations will cause paf to go high at the conditions described in table 3. if further read operations occur, without write operations, pae will go low when there are n words in the queue, where n is the empty offset value. continuing read operations will cause the queue to become empty. when the last word has been read from the queue, the ef will go low inhibiting further read operations. ren is ignored when the queue is empty. when configured in idt standard mode, the ef and ff outputs are double register-buffered outputs. idt standard mode is available when the device is configured in both single data rate and double data rate mode. relevant timing diagrams for idt standard mode can be found in figure 12, write cycle and full flag timing (idt standard mode) . first word fall through mode (fwft) in this mode, the status flags or , ir , pae , and paf operate in the manner outlined in table 4. to write data into to the queue, wcs must be low. data presented to the d[39:0] lines will be clocked into the queue on subsequent transitions of wclk. after the first write is performed, the output ready ( or ) flag will go low. subsequent writes will continue to fill up the queue. pae will go high after n + 2 words have been loaded into the queue, where n is the empty offset value. the default setting for these values are listed in table 4. this parameter is also user programmable as described in the serial writing and reading of offset registers section. continuing to write data into the queue without performing read operations will cause the programmable almost-full flag ( paf ) to go low. again, if no reads are performed, the paf will go low after (8,193-m) writes for the IDT72T51248, (16,385-m) writes for the idt72t51258, and (32,769-m) writes for the idt72t51268. this is assuming the i/o bus width is configured to x40. if the i/o is x20, then paf will go low after (16,385-m) writes for the IDT72T51248, (32,769-m) writes for the idt72t51258, and (65,537-m) writes for the idt72t51268. if the i/o is x10, then paf will go low after (32,769-m) writes for the IDT72T51248, (65,537-m) writes for the idt72t51258, and (131,073-m) writes for the idt72t51268. the offset ?m? is the full offset value. the default setting for these values are listed in table 4. this parameter is also user programmable. see the section on serial writing and reading of offset registers for details. when the queue is full, the input ready ( ir ) will go low, inhibiting further write operations. if no reads are performed after a reset, ir will go low after d writes to the queue. if the i/o bus width is configured to x40, then d = 8,193 writes for the IDT72T51248, 16,385 writes for the idt72t51258, and 32,769 writes for the idt72t51268. if the i/o is x20, then d = 16,385 writes for the IDT72T51248, 32,769 writes for the idt72t51258, and 65,537 writes for the idt72t51268. if the i/o is x10, then d = 32,769 writes for the IDT72T51248, 65,537 writes for the idt72t51258, and 131,073 writes for the idt72t51268. if the queue is full, the first read operation will cause ir to go high after two clock cycles. subsequent read operations will cause paf to go high at the conditions described in table 4. if further read operations occur, without write operations, pae will go low when there are n words in the queue, where n is the empty offset value. continuing read operations will cause the queue to become empty. then the last word has been read from the queue, the or will go high inhibiting further read operations. rcs is ignored when the queue is empty. when configured in fwft mode, the or flag output is triple register-buffered and the ir flag output is double register-buffered. relevant timing diagrams for fwft mode can be found in figure 16, write timing in fwft mode . hstl/lvttl i/o the inputs and outputs of this device can be configured for either lvttl or hstl/ehstl operation. if the iosel pin is high during master reset, then all applicable lvttl or hstl signals will be configured for hstl/ehstl operating voltage levels. to select between hstl or ehstl v ref must be driven to ? v ref . typically a logic high in hstl would be v ref +300mv and a logic low would be v ref ? 300mv. if the iosel pin is low during master reset, then all applicable lvttl or hstl signals will be configured for lvttl operating voltage levels. in this configuration v ref must be set to the static core voltage of 2.5v. table 5 illustrates which pins are and are not associated with this feature. note that all ?static pins? must be tied to v cc or gnd. these pins are cmos only and are purely device configuration pins. note the iosel pin should be tied high or low and cannot toggle before and after master reset. lvttl/hstl/ehstl static cmos signals write port read port jtag control pins serial port static pins d[39:0] cef / cor tck fsel[1:0] sclk iosel wclk ef 0/1/2/3 trst is[1:0] sren iw[1:0] wen or 0/1/2/3 tms os[1:0] swen ow[1:0] ff 0/1/2/3 erclk tdi pd fwft/si rddr wcs oe tdo mrs sdo wddr cff / cir pae 0/1/2/3 prs paf 0/1/2/3 q[39:0] fwft/si rclk rcs ren eren table 5 i/o voltage level configuration
18 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 bus matching the write and read port has bus-matching capability such that the input and output bus can be either 10 bits, 20 bits or 40 bits wide. the bus width of both the input and output port is determined during master reset using the input and output width setup pins (iw[1:0], ow[1:0]). the selected port width is applied to all four queue ports, such that all four queues will be configured for either x10, x20 or x40 bus widths. when writing or reading data from a queue the number of memory locations available to be written or read will depend on the bus width selected and the density of the device. if the write/read port is 10 bits wide, this provides the user with a queue depth of 32,768 x 10 for the IDT72T51248, 65,536 x 10 for the idt72t51258, or 131,072 x 10 for the idt72t51268. if the write/read port is 20 bits wide, this provides the user with a queue depth of 16,384 x 20 for the IDT72T51248, 32,768 x 20 for the idt72t51258, or 65,536 x 20 for the idt72t51268. if the write/read port is 40 bits wide, this provides the user with a queue depth of 8,192 x 40 for the IDT72T51248, 16,384 x 40 for the idt72t51258, or 32,768 x 40 for the idt72t51268. the queue depths will always have a fixed density of 327,680 bits for the IDT72T51248, 655,360 bits for the idt72t51258 and 1,310,072 bits for the idt72t51268 regardless of bus-width configuration on the write/read port. when the device is operating in double data rate, the word is twice as large as in single data rate since one word consists of both the rising and falling edge of clock. therefore in ddr, the queue depths will be half of what it is mentioned above. for instance, if the write/read port is 10 bits wide, the depth of each queue is 16,384 x 10 for the IDT72T51248, 32,768 x 10 for the idt72t51258, or 65,536 x 10 for the idt72t51268. see figure 5, bus-matching byte arrangement for more information.
19 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 6159 drw10 x40 input to x10 output for queue0 1st: read from queues d39-d30 d29-d20 d19-d10 d9-d0 a 1st: write to queues a 3rd: read from queues b 2nd: read from queues c 1st: read from queues a b lll h l is1 is0 iw1 lh iw0 l 4th: read from queues d os1 os0 ow1 ow0 2nd: read from queues d byte order on input port: byte order on output port: b c d q39-q30 q29-q20 q19-q10 q9-q0 q39-q30 q29-q20 q19-q10 q9-q0 l os1 os0 ow1 ll ow0 l byte order on output port: c x40 input to x20 output for queue0 llh l os1 os0 ow1 ow0 byte order on output port: x40 input to x40 output for queue0 q39-q30 q29-q20 q19-q10 q9-q0 a b c d 1st: read from queues figure 5. bus-matching byte arrangement notes: = outputs are high-impedanced. = inputs set to gnd.
20 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 6159 drw11 1st: read from queues a lhl l os1 os0 ow1 ow0 2nd: read from queues byte order on output port: b x20 input to x10 output for queue1 lhh l os1 os0 ow1 ow0 byte order on output port: x20 input to x40 output for queue1 q39-q30 q29-q20 q19-q10 q9-q0 a b c d 1st: read from queues 1st: write to queues a b lhl h is1 is0 iw1 iw0 2nd: write to queues d byte order on input port: d39-d30 d29-d20 d19-d10 d9-d0 c lhl h os1 os0 ow1 ow0 byte order on output port: x20 input to x20 output for queue1 q39-q30 q29-q20 q19-q10 q9-q0 a b 1st: read from queues q39-q30 q29-q20 q19-q10 q9-q0 3rd: read from queues c 4th: read from queues d c d 2nd: read from queues figure 5. bus-matching byte arrangement (continued) notes: = outputs are high-impedanced. = inputs set to gnd.
21 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 6159 drw12 1st: read from queues a hl l l os1 os0 ow1 ow0 2nd: read from queues byte order on output port: b x10 input to x10 output for queue2 hl h l os1 os0 ow1 ow0 byte order on output port: x10 input to x40 output for queue2 q39-q30 q29-q20 q19-q10 q9-q0 a b c d 1st: read from queues 1st: write to queues a hl l l is1 is0 iw1 iw0 2nd: write to queues byte order on input port: d39-d30 d29-d20 d19-d10 d9-d0 b hl l h os1 os0 ow1 ow0 byte order on output port: x10 input to x20 output for queue2 q39-q30 q29-q20 q19-q10 q9-q0 a b 1st: read from queues q39-q30 q29-q20 q19-q10 q9-q0 3rd: write to queues c d 4th: write to queues 3rd: read from queues c 4th: read from queues d c d 2nd: read from queues figure 5. bus-matching byte arrangement (continued) notes: = outputs are in high-impedanced. = inputs are set to gnd.
22 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 write port operation the input select pins (is[1:0]) determine which one of the four queues the input bus will write data into. the input select pins are sampled on the rising edge of every wclk, and may change on every clock edge. there is no delay switching from one queue to another. note, there is a two-stage pipe-line on both the read and write data paths causing a two-cycle latency on each operation. data can be written on each clock regardless of the queue selected. a write operation will not be physically written into the queue until the second clock. provided data is written every clock, following the first two-cycle latency, data will reach the respective queue on every clock as well. data will be written on the rising (and falling in ddr) edge of write clock provided wen and wcs are active on the rising edge of the write clock. note in double data rate the setup and hold times of the write enables and write chip selects are sampled with respect to the rising edge of its respective write clock only. the falling edge of wclk does not sample the write enable and write chip select. when selecting a queue for write operations the next word can be written to that queue immediately on the next clock edge after the new queue is selected. for example, if is[1:0] is set to 01 (queue1) on wclk edge 0, then on wclk edge 1 (next read clock edge) data can be written to queue1 if wen and wcs are enabled. in fwft mode the first word written to a selected queue will automatically be placed onto the output bus regardless of the state of the corresponding ren , provided that the selected queue was empty and its corresponding output ready flag was inactive. the data will take four clocks to reach the out-put taking into account the two-cycle write and two-cycle read pipeline. this occurs due to the nature of the fwft flag timing. subsequent writes to the queue that is not empty will not fall through to the output bus providing rcs is low and rclk toggles. in idt standard mode, every word, including the first word, must be accessed by the read enable and read chip select. read port operation the output select pins (os[1:0]) determine which one of the four queues the output bus will read data from. the output select pins are sampled on the rising edge of every rclk, and may change on every clock edge. note, there is a two-stage pipe-line on both the read and write data paths causing a two-cycle latency on each operation. data can be read on each clock regardless of the queue selected. a read operation will not be physically presented to the data pins until the second clock. provided data is read every clock, following the first two-cycle latency, data will reach the data bus on every clock as well. data will be read on the rising (and falling in ddr) edge of read clock provided read enable and read chip select are active (low). when selecting a queue for read operations the new word read from that queue will be available immediately on the next clock edge after the new queue is selected. for example, if os[1:0] is set to 01 (queue1) on rclk edge 0, then on rclk edge 1 (next read clock edge) data can be read from queue1 if ren and rcs are enabled. data is presented on the second rclk. in fwft mode, the first word written to a selected queue will automatically be placed onto the output bus of that respective queue regardless of the state of the corresponding read enable, provided that the selected queue was empty and its corresponding output ready flag was inactive. the data will take four clocks to reach the out-put taking into account the two-cycle write and two-cycle read pipeline. this occurs due to the nature of the fwft flag timing. subsequent writes to the queue that is not empty will not fall through to the output bus. note in fwft mode, during a queue selection the next word available in the queue will automatically fall through to the output bus regardless of the read enable and read chip select. in idt standard mode, every word including the first word must be accessed by the ren and rcs . unlike fwft mode, during a queue selection the next word available in the queue will not automatically fall through to the output bus. the previous word that was read out of the read port will remain on the output bus if the ren is high an rcs is low, if rcs is high the output will be high-z.
23 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 signal descriptions inputs: data input bus (d[39:0]) the data input bus can be 40, 20, or 10 bits wide. d[39:0] are data inputs for the 40-bit wide data bus, d[19:0] are data inputs for 20-bit wide data bus, and d[9:0] are data inputs for the 10-bit wide data bus. master reset ( mrs ) there is a single master reset available for all internal queues in this device. a master reset is accomplished whenever the mrs input is taken to a low state. this operation sets the internal read and write pointers of all queues to the first location in memory. the programmable almost empty flag will go low and the almost full flags will go high. if fwft/si signal is low during master reset then idt standard mode is selected. this mode utilizes the empty and full status flags from the ef / or and ff / ir dual-purpose pin. during master reset, all empty flags will be set to low and all full flags will be set to high. if fwft/si signal is high during master reset, then the first word fall through mode is selected. this mode utilizes the input read and output ready status flags from the ef / or and ff / ir dual-purpose pin. during master reset, all input ready flags will be set to low and all output ready flags will be set to high. all device configuration pins such as ow[1:0], iw[1:0], is[1:0], os[1:0], wddr, rddr, iosel, fsel[1:0] and fwft/si needs to be defined before the master reset cycle. during a master reset the output register is initialized to all zeros. if the output enable(s) are low during master reset, then the output bus will be low. if the output enable(s) are high during master reset, then the output bus will be in high-impedance. rcs has no affect on the data outputs during master reset. if the output width ow[1:0] is configured to x10 or x20, then the unused outputs will be in high-impedance. a master reset is required after power up before a write operation to any queue can take place. master reset is an asynchronous signal and thus the read and write clocks can be free- running or idle during master reset. see figure 10, master reset timing , for the associated timing diagram. partial reset ( prs 0/1/2/3) a partial reset is a means by which the user can reset both the read and write pointers of each individual queue inside the device without changing the queue?s configuration. there are four dedicated partial reset signals that each correspond to an individual queue. there are restrictions as to when partial reset can be performed in either operating modes. during partial reset, the internal read and write pointers are set to the first location in memory, pae goes low and paf goes high. whichever timing mode was active at the time of partial reset will remain active after partial reset. if idt standard mode is active, then ff will go high and ef will go low. if the first word fall through mode is active, then or will go high and ir will go low. following partial reset, all values held in the offset registers remain unchanged. the output registers are initialized to all zeros. all other configura- tions set up during master reset remain unchanged. prs is an asynchronous signal. see figure 11, partial reset timing , for the associated timing diagram. first word fall through/serial in (fwft/si) this is a dual purpose pin. during master reset, the state of the fwft/si input determines whether the device will operate in idt standard mode or first word fall through (fwft) mode. if fwft/si is low before the falling edge of master reset, then idt standard mode will be selected. this mode uses the empty flag ( ef ) to indicate whether or not there are any words present in the queues. it also uses the full flag function ( ff ) to indicate whether or not the queues has any free space for writing. in idt standard mode, every word read from the queue, including the first, must be requested using the read enable ( ren ), read chip select ( rcs ) and rclk. if fwft/si is high before the falling edge of master reset, then fwft mode will be selected. this mode uses output ready ( or ) to indicate whether or not there is valid data at the data outputs (qn). it also uses input ready ( ir ) to indicate whether or not the queues have any free space for writing. in the fwft mode, the first word written to an empty queue goes directly to output qn after three rclk rising edges, provided that the first rclk meets t skew parameters. there will be a one rclk cycle delay if t skew is not met. ren and rcs do not need to be enabled. subsequent words must be accessed using the ren , rcs , and rclk. if rcs is high, the output will be in high-impedance. the state of the fwft/si input must be kept at the present state for the minimum of the reset recovery time (t rsr ) after master reset. after this time, the fwft/ si acts as a serial input for loading pae and paf offsets into the programmable offset registers. the serial input is used in conjunction with sclk, swen , sren , and sdo to access the offset registers. serial programming using the fwft/ si pin functions the same way in both idt standard and fwft modes. write clock (wclk) the write clock is used to write data to each individual queue within the device. a write cycle is initiated on the rising and/or falling edge of the wclk input. if the write double data rate (wddr) mode pin is tied high during master reset, data will be written on both the rising and falling edge of wclk, provided that wen and wcs are enabled. if wddr is tied low, data will be written only on the rising edge of wclk provided that wen and wcs are enabled. data setup and hold times must be met with respect to the low-to-high (and high-to-low in ddr) transition of the write clock(s). it is permissible to stop the write clock(s). note that while the write clocks are idle, the ff / ir and paf flags will not be updated. write enable ( wen ) the write enable controls whether or not data will be written into the selected queue memory. when the write enable input is low on the rising edge of wclk in single data rate, data is loaded on the rising edge of every wclk cycle, provided the device is not full and the write chip select ( wcs ) is enabled. the setup and hold times are referenced with respect to the rising edge of wclk only. when the write enable input is low on the rising edge of wclk in double data rate, data is loaded into the selected queue on the rising and falling edge of every wclk cycle, provided the device is not full and the write chip select ( wcs ) is enabled. in this mode, the data setup and hold times are referenced with respect to the rising and falling edge of wclk. note that wen and wcs are sampled only on the rising edge of wclk in either data rate mode. data is stored in the queues memory sequentially and independently of any ongoing read operation. when the write enable and write chip select are high, no new data is written into the corresponding queue on each wclk cycle. write chip select ( wcs ) the write chip selects disables the write port inputs if it is held high. to perform normal write operations the write chip select must be enabled, held low. when the write chip select is low on the rising edge of wclk in single data rate, data is loaded on the rising edge of every wclk cycle, provided the device is not full and the write enable ( wen ) is low. when the wcs is low
24 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 on the rising edge of wclk, in double data rate, data is loaded into the selected queue on the rising and falling edge of every wclk cycle, provided the device is not full and the write enable ( wen ) is low. when the write chip select is high on the rising edge of wclk in single data rate, the write port is disabled and no words are written on the rising edge of wclk into the queue, even if wen is low. if the write chip select is high on the rising edge of wclk in double data rate, the write port is also disabled and no words are written on the rising and falling edge of wclk into the queue, even if wen is low. note that wcs is sampled on the rising edge of wclk only in either data rate mode. write double data rate (wddr) when the write double data rate (wddr) pin is high prior to master reset, the write port will be set to double data rate mode. in this mode, all write operations are based on the rising and falling edge of the write clocks, provided that write enables and write chip selects are low for the rising clock edges. in double data rate the write enable signals are sampled with respect to the rising edge of write clock only, and a word will be written on both the rising and falling edge of write clock regardless of whether or not write enable is active on the falling edge of write clock. when wddr is low, the write port will be set to single data rate mode. in this mode, all write operations are based on only the rising edge of the write clock, provided that wen and wcs are low during the rising edge of write clock. this pin should be tied high or low and cannot toggle before or after master reset. read clock (rclk) the read clock is used to read data from each individual queue within the device. a read cycle is initiated on the rising and/or falling edge of the rclk input. if the read double data rate (rddr) mode pin is tied high at master reset, data will be read on both the rising and falling edge of rclk, provided that ren and rcs are enabled. if rddr is tied low at master reset, data will be read only on the rising edge of rclk provided that ren and rcs are enabled. there is an associated data access time (t a ) for the data to be read out of the queues. it is permissible to stop the read clocks. note that while the read clocks are idle, the ef / or and pae flags will not be updated. read enable ( ren ) the read enable controls whether or not data will be read out of the memory. when the read enable input is low on the rising edge of rclk in single data rate, data will be read on the rising edge of every rclk cycle, provided the device is not empty and the read chip select ( rcs ) is enabled. the associated data access time (t a ) is referenced with respect to the rising edge of rclk. when the read enable input is low on the rising edge of rclk in double data rate, data will be read on the rising and falling edge of every rclk cycle, provided the device is not empty and rcs is enabled. in this mode, the data access times are referenced with respect to the rising and falling edges of rclk. note that ren is sampled only on the rising edge of rclk in either data rate mode. data is stored in the queues sequentially and independently of any ongoing write operation. when the ren and rcs are high, no new data is read on each rclk cycle. to prevent reading from an empty queue in the idt standard mode, the empty flag of each queue will go low, with respect to rclk, when the total number of words in the queue has been read out, thus inhibiting further read operations. upon the completion of a valid write cycle, the empty flag will go high with respect to rclk, two cycles later, thus allowing another read to occur given that t skew between wclk and rclk is met. read chip select ( rcs ) the read chip select input provides synchronous control of the read port of the device. when the read chip select is held low, the next rising edge of the corresponding rclk will enable the output bus. when the read chip select goes high, the next rising edge of rclk will send the output bus into high- impedance and prevent that rclk from initiating a read, regardless of the state of ren . during a master or partial reset the read chip select input has no effect on the output bus, output enable ( oe ) is the only input that provides high- impedance control of the output bus. if output enable is low, the data outputs will be active regardless of read chip select until the first rising edge of rclk after a reset is complete. afterwards if read chip select is high the data outputs will go to high-impedance. the read chip select input does not affect the updating of the flags. for example, when the first word is written to any/all empty queues, the empty flags will still go from low to high based on a rising edge of the rclk, regardless of the state of the read chip select input. also, when operating the queue in fwft mode the first word written to any/all empty queues will still be clocked through to the output bus on the third rising edge of rclk(s), regardless of the state of read chip select inputs, assuming that the t skew parameter is met. for this reason the user should pay extra attention to the read chip selects when a data word is written to any/all empty queues in fwft mode. if the read chip select input is high when an empty queue is written into, the first word will fall through to the output register but will not be available on the outputs because the bus is in high-impedance. the user must enable the read chip selects on the next rising edge of rclk to access this first word. see figure 28, echo read clock and read enable operation (idt standard mode). see figure 29, echo rclk and echo read enable operation (fwft mode). read double data rate (rddr) when the read double data rate (rddr) pin tied high, the read port will be set to double data rate mode sampled during master reset. in this mode, all read operations are based on the rising and falling edge of the read clocks, provided that read enables and read chip selects are low. in ddr mode the read enable signals are sampled with respect to the rising edge of read clock only, and a word will be read from both the rising and falling edge of read clock regardless of whether or not read enable and read chip select are active on the falling edge of read clock. when rddr is tied low during master reset, the read port will be set to single data rate mode. in this mode, all read operations are based on only the rising edge of the rclk, provided that ren and rcs are low during the rising edge of read clock. this pin should be tied high or low and cannot toggle before and after master reset. output enable ( oe ) the output enable controls whether the output bus will be in active or high- impedance state. when the output enable input is low, the output bus becomes active and drives the data currently in the output register. when the output enable input ( oe ) is high, the output bus goes into high-impedance. during master or partial reset the output enable is the only input that can place the output data bus into high-impedance. during reset the read chip select input has no effect on the output data bus. i/o select (iosel) the inputs and outputs of this device can be configured for either lvttl or hstl/ehstl operation. if the iosel pin is high during master reset, then all applicable lvttl or hstl signals will be configured for hstl/ehstl operating voltage levels. to select between hstl or ehstl v ref must be driven to ? v ddq .
25 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 if the iosel pin is low during master reset, then all applicable lvttl or hstl signals will be configured for lvttl operat ing voltage levels. in this configuration v ddq should be set to the static core voltage of the 2.5v and v ref will be ? v ddq . this pin should be tied high or low and cannot toggle before or after master reset. please refer to table 5 for a list of applicable lvttl/hstl/ehstl signals. power down ( pd ) this device has a power down feature intended for reducing power consumption for hstl/ehstl configured inputs when the device is idle for a long period of time. by entering the power down state certain inputs can be disabled, thereby significantly reducing the power consumption of the part. all wen and ren signals must be disabled for a minimum of four wclk and rclk cycles before activating the power down signal. the power down signal is asynchronous and needs to be held low throughout the desired power down time. during power down, the following conditions for the inputs/outputs signals are: ? all data in queue(s) are retained. ? all data inputs become inactive. ? all write and read pointers maintain their last value before power down. ? all enables, chip selects, and clock input pins become inactive. ? ? ? ? ? all data outputs become inactive and enter high-impedance state. ? ? ? ? ? all flag outputs will maintain their current states before power down. ? ? ? ? ? all programmable flag offsets maintain their values. ? ? ? ? ? all echo clock and enable will become inactive and enter high- impedance state. ? ? ? ? ? the serial programming and jtag port will become inactive and enter high-impedance state. ? ? ? ? ? all setup and configuration cmos static inputs are not affected, as these pins are tied to a known value and do not toggle during operation. all internal counters, registers, and flags will remain unchanged and maintain their current state prior to power down. clock inputs can be continuous and free- running during power down, but will have no affect on the part. however, it is recommended that the clock inputs be low when the power down is active. to exit power down state and resume normal operations, disable the power down signal by bringing it high. there must be a minimum of 1 s waiting period before read and write operations can resume. the device will continue from where it had stopped, no form of reset is required after exiting power down state. the power down feature does not provide any power savings when the inputs are configured for lvttl operation. however, it will reduce the current for i/os that are not tied directly to v cc or gnd. see figure 35, power down operation , for the associated timing diagram. serial clock (sclk) the serial clock is used to load data to, and read data from, the programmable offset registers. data from the serial input signal (fwft/si) can be loaded into the offset registers on the rising edge of sclk provided that the serial write enable ( swen ) signal is low. data can be read from the offset registers via the serial data output (sdo) signal on the rising edge of sclk provided that sren is low. the serial clock can operate at a maximum frequency of 10mhz. the read operation is non-destructive. the write operation will change registers on each rising edge of sclk serial write enable ( swen ) the serial write enable input is an enable used for serial programming of the programmable offset registers. it is used in conjunction with the serial input (fwft/si) and serial clock (sclk) when programming the offset registers. when the serial write enable is low, data at the serial input is loaded into the offset register, one bit for each low-to-high transition of sclk. when serial write enable is high, the offset registers retain the previous settings and no offsets are loaded. serial write enable functions the same way in both idt standard and fwft modes. each bit that is loaded into the offset register is serially shifted through the register so each rising edge of sclk will change the value of the offsets. serial read enable ( sren ) the serial read enable input is an enable used for reading the value of the programmable offset registers. it is used in conjunction with the serial data output (sdo) and serial clock (sclk) when reading the offset registers. when the serial read enable is low, data at the serial data output can be read from the offset register, one bit for each low-to-high transition of sclk. when serial read enable is high, the reading of the offset registers will stop. whenever serial read enable ( sren ) is activated values in the offset registers are read starting from the first location in the offset registers. on a high to low transition, the sren copies the values in the offset registers directly into a serial scan out register. sren must be kept low in order to read the entire contents of the offset register. if at any point sren is toggled from high to low, another copy function from the offset register to the serial scan out register will occur. serial read enable functions the same way in both idt standard and fwft modes.
26 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 outputs data output bus (q[39:0]) the data output bus can be 40, 20, or 10 bits wide. q[39:0] are data outputs for the 40-bit wide data bus, q[19:0] are data outputs for 20-bit wide data bus, and q[9:0] are data outputs for the 10-bit wide data bus. in fwft mode, when switching from one queue to another, the data of the newly selected queue will always be present on the output bus immediately, two rising rclk edges after os[1:0] is selected regardless of whether or not read enable and read chip select are active. empty/output ready flag ( ef / or 0/1/2/3) there are four empty/output ready flags available in this device, each corresponding to the individual queues in memory. this is a dual-purpose pin that is determined based on the state of the fwft/si pin during master reset for selecting one of the, two timing modes of this device. in the idt standard mode, the empty flags are selected. when an individual queue is empty, its empty flag will go low, inhibiting further read operations from that queue. when the empty flag is high, the individual queue is not empty and valid read operations can be applied. see figure 18, read cycle, empty flag and first word latency timing (idt standard mode) , for the relevant timing information. also see table 3 ?status flags for idt standard mode? for the truth table of the empty flags. in fwft mode, the output ready flags are selected. output ready flags ( or ) go low at the same time that the first word written to an empty queue appears on the outputs, which is a minimum of three read clock cycles provided the rclk and wclk meets the t skew parameter. or stays low after the rclk low- to-high transitions that shifts the last word from the queue to the outputs. or goes high when an enabled read operation is performed from an empty queue. the previous data stays on the outputs, indicating the last word was read. further data reads are inhibited until a new word is on the bus when or goes low again. see figure 22, read timing at full boundary (fwft mode ), for the relevant timing information. also see table 4 ?status flags for fwft mode? for the truth table of the empty flags. the empty/output ready flags are synchronous and updated on the rising edge of rclk. in idt standard mode, the flags are double register-buffered outputs. in fwft mode, the flag is triple register-buffered outputs. the four empty flags operate independent of one another and always indicate the respective queue's status. composite empty/output ready flag ( cef / cor ) this status pin is used to determine the empty state of the current queue selected. the composite empty/output ready flag represents the state of the queue selected on the read port, such that the user does not have to monitor each individual queues? empty/output ready flags. the timing of the composite empty/output ready flag differs in idt standard and fwft modes. in idt standard mode, when switching from one queue to another, the composite empty flag will update to the status of the newly selected queue one rclk cycle after the rising edge of rclk that made the new queue selection. in fwft mode, the composite output ready flag will update to the status of the newly selected queue on two clock cycles after the rising edge of rclk that made the new queue selection. see figure 23, composite empty flag (idt standard mode), for the associated timing diagram. see table 3 and 4 ?status flags for idt standard and fwft mode ? for the truth table of the composite empty flag. full/input ready flag ( ff / ir 0/1/2/3) there are four full/input ready flags available in this device, each corresponding to the individual queues in memory. this is a dual-purpose pin that is determined based on the state of the fwft/si pin during master reset for selecting the two timing modes of this device. in the idt standard mode, the full flags are selected. when an individual queue is full, its full flags will go low after the rising edge of wclk that wrote the last word, thus inhibiting further write operations to the queue. when the full flag is high, the individual queue is not full and valid write operations can be applied. see figure 12, write cycle, full flag timing (idt standard mode) , for the associated timing diagram. also see table 3 ?status flags for idt standard mode? for the truth table of the full flags. in fwft mode, the input ready flags are selected. input ready flags go low when there is adequate memory space in the queues for writing in data. the input ready flags go high after the rising edge of wclk that wrote the last word, when there are no free spaces available for writing in data. see figure 16, write timing (fwft mode ), for the associated timing information. also see table 4 ?status flags for fwft mode? for the truth table of the full flags. the input ready status not only measures the contents of the queues, but also counts the presence of a word in the output register. thus, in fwft mode, the total number of writes necessary to make ir high is one greater than needed to set the ff (low) in idt standard mode. ff / ir is synchronous and updated on the rising edge of wclk. ff / ir are double register-buffered outputs. the four full flags operate independent of one another. to prevent data overflow in the idt standard mode, the full flag of each queue will go low with respect to wclk, when the maximum number of words has been written into the queue, thus inhibiting further write operations. upon the completion of a valid read cycle, the full flag will go high with respect to wclk two cycles later, thus allowing another write to occur assuming t skew has been met. to prevent data overflow in the fwft mode, the input ready flag of each queue will go high with respect to wclk, when the maximum number of words has been written into the queue, thus inhibiting further write operations. upon the completion of a valid read cycle, the input ready flag will go low with respect to wclk two cycles later, thus allowing another write to occur assuming t skew has been met. composite full/input ready flag ( cff / cir ) this status pin is used to determine the full state of the current queue selected. the composite full/input ready flag represents the state of the queue selected on the write port, such that the user does not have to monitor each individual queues? full/input ready flag. when switching from one queue to another, the composite full/input ready flag will update to the status of the newly selected queue one wclk cycle after the rising edge of wclk that made the new queue selection, regardless of which timing mode the device is operating in. see figure 25, composite full flag (idt standard mode) , for the relevant associated timing diagram. see table 3 and 4 ?status flags for idt standard and fwft mode ? for the truth table of the composite full flag programmable almost empty flag ( pae 0/1/2/3) there are four programmable almost empty flags available in this device, each corresponding to the individual queues in memory. the programmable almost empty flag is an additional status flag that notifies the user when the queue is near empty. the user may utilize this feature as an early indicator as to when the queue will become empty. in idt standard mode, pae will go low when there are n words or less in the queue. in fwft mode, the pae will go low when there are n-1 words or less in the queue. the offset ?n? is the empty offset value. the default setting for this value is stated in table 2. since there are four internal queues hence four pae offset values, n0, n1, n2, and n3. the four programmable almost empty flags operate independent of one another.
27 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 programmable almost full flag ( paf 0/1/2/3) there are four programmable almost full flags available in this device, each corresponding to the individual queues in memory. the programmable almost full flag is an additional status flag that notifies the user when the queue is nearly full. the user may utilize this feature as an early indicator as to when the queue will not be able to accept any more data and thus prevent data from being dropped. in idt standard mode, if no reads are performed after master reset, paf will go low after (d-m) (d meaning the density of the particular device) words are written to the queue. in fwft mode, paf will go low after (d+1- m) words are written to the queue. the offset ?m? is the full offset value. the default setting for this value is stated in table 2. since there are four internal queues hence four paf offset values, m0, m1, m2, and m3. the four programmable almost full flags operate independent of one another. table 6 t skew measurement data port status flags t skew measurement datasheet configuration parameter ddr input ef / or negative edge wclk to t skew2 to positive edge rclk ddr output ff / ir negative edge rclk to t skew2 positive edge wclk pae negative edge wclk to t skew3 positive edge rclk paf negative edge rclk to t skew3 positive edge wclk ddr input ef / or negative edge wclk to t skew2 to positive edge rclk sdr output ff / ir positive edge rclk to t skew1 positive edge wclk pae negative edge wclk to t skew3 positive edge rclk paf positive edge rclk to t skew3 positive edge wclk sdr input ef / or positive edge wclk to t skew1 to positive edge rclk ddr output ff / ir negative edge rclk to t skew2 positive edge wclk pae positive edge wclk to t skew3 positive edge rclk paf negative edge rclk to t skew3 positive edge wclk sdr input ef / or positive edge wclk to t skew1 to positive edge rclk sdr output ff / ir positive edge rclk to t skew1 positive edge wclk pae positive edge wclk to t skew3 positive edge rclk paf positive edge rclk to t skew3 positive edge wclk
28 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 echo read clock (erclk) the echo read clock is a free-running clock output, that will always follow the rclk input regardless of the read enables and read chip selects. the erclk output follows the rclk input with an associated delay. this delay provides the user with a more effective read clock source when reading data from the output bus. this is especially helpful at high speeds when variables within the device may cause changes in the data access times. these variations in access time may be caused by ambient temperature, supply voltage, or device characteristics. any variations effecting the data access time will also have a corresponding effect on the echo read clock output produced by the device, therefore the echo read clock output level transitions should always be at the same position in time relative to the data outputs. note, that echo read clock is guaranteed by design to be slower than the slowest data outputs. refer to figure 6, echo read clock figure 6. echo read clock and data output relationship notes: 1. ren and rcs are low. oe is low. 2. t erclk > t a , guaranteed by design. 3. qslowest is the data output with the slowest access time, t a . in sdr mode. 4. time, t d is greater than zero, guaranteed by design. 5. qslowest is the data output with the slowest access time, t a . in ddr mode. 6159 drw13 erclk t a t d q slowest (3) rclk t erclk t a t d q slowest (5) and data output relationship , figure 28, echo read clock and read enable operation in double data rate mode and figure 29, echo rclk and echo ren operation for timing information. echo read enable ( eren ) the echo read enable output is provided to be used in conjunction with the echo read clock and provides the device receiving data from the queue with a more effective scheme for reading the queues? data. the echo read enable output is controlled by internal logic that becomes active for the read clock cycle that a new word is read out of the queue. that is, a rising edge of read clock will cause echo read enable to go low, if both read enable and read chip select are active and the queue is not empty. in other words, every cycle samples the output bus and drives eren output to the correct value.
29 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 tdo tdo tdi/ tms tck trst t doh notes to diagram: t1 = t tcklow t2 = t tckhigh t3 = trst (reset pulse width) t4 = trsr (reset recovery) 6159 drw14 t 3 t 4 t 1 t 2 t tck t dh t ds t do figure 7. standard jtag timing parameter symbol test conditions min. max. units jtag clock input period t tck - 100 - ns jtag clock high t tckhigh -40-ns jtag clock low t tcklow -40-ns jtag reset t rst -50-ns jtag reset recovery t rsr -50-ns jtag ac electrical characteristics ( v cc = 2.5v 5%; tambient (industrial) = 0 c to +85 c) note: 1. 50pf loading on external output signals. system interface parameters IDT72T51248 idt72t51258 idt72t51268 parameter symbol test conditions min. max. units data output t do (1) -20ns data output hold t doh (1) 0-ns data input t ds t rise=3ns 10 - ns t dh t fall=3ns 10 -
30 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 jtag timing specifications (ieee 1149.1 compliant) the jtag test port in this device is fully compliant with the ieee standard test access port (ieee 1149.1) specifications. five additional pins (tdi, tdo, tms, tck and trst ) are provided to support the jtag boundary scan interface. note that idt provides appropriate boundary scan description language program files for these devices. the standard jtag interface consists of seven basic elements: ? test access port (tap) ? tap controller ? instruction register (ir) ? data register port (dr) ? bypass register (byr) ? id code register ? flag programming the following sections provide a brief description of each element. for a complete description refer to the ieee standard test access port specification (ieee std. 1149.1-1990). the figure below shows the standard boundary-scan architecture figure 8. jtag architecture test access port (tap) the tap interface is a general-purpose port that provides access to the internal jtag state machine. it consists of four input ports (tclk, tms, tdi, trst ) and one output port (tdo). the tap controller the tap controller is a synchronous finite state machine that responds to tms and tclk signals to generate clock and control signals to the instruction and data registers for capture and updating of data passed through the tdi serial input. in pad in pad incell incell core logic outcell outcell out pad out pad all outputs all inputs eg: dins, clks (bsdl file describes the chain order) id bypass instruction register ta p tms tdi tck trst instruction select enable tdo 6159 drw15 flag offset chain
31 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 refer to the ieee standard test access port specification (ieee std. 1149.1) for the full state diagram all state transitions within the tap controller occur at the rising edge of the tclk pulse. the tms signal level (0 or 1) determines the state progression that occurs on each tclk rising edge. the tap controller takes precedence over the queue operation and must be reset after power up of the device. see trst description for more details on tap controller reset. test-logic-reset all test logic is disabled in this controller state enabling the normal operation of the ic. the tap controller state machine is designed in such a way that, no matter what the initial state of the controller is, the test-logic-reset state can be entered by holding tms at high and pulsing tck five times. this is the reason why the test reset ( trst ) pin is optional. run-test-idle in this controller state, the test logic in the ic is active only if certain instructions are present. for example, if an instruction activates the self test, then it will be executed when the controller enters this state. the test logic in the ic is idle otherwise. select-dr-scan this is a controller state where the decision to enter the data path or the select-ir-scan state is made. select-ir-scan this is a controller state where the decision to enter the instruction path is made. the controller can return to the test-logic-reset state other wise. figure 9. tap controller state diagram capture-ir in this controller state, the shift register bank in the instruction register parallel loads a pattern of fixed values on the rising edge of tck. the last two significant bits are always required to be ?01?. shift-ir in this controller state, the instruction register gets connected between tdi and tdo, and the captured pattern gets shifted on each rising edge of tck. the instruction available on the tdi pin is also shifted in to the instruction register. tdo changes on the falling edge of tck. exit1-ir this is a controller state where a decision to enter either the pause- ir state or update-ir state is made. pause-ir this state is provided in order to allow the shifting of instruction register to be temporarily halted. exit2-dr this is a controller state where a decision to enter either the shift- ir state or update-ir state is made. update-ir in this controller state, the instruction in the instruction register scan chain is latched in to the register of the instruction register on every falling edge of tck. this instruction also becomes the current instruction once it is latched. capture-dr in this controller state, the data is parallel loaded in to the data registers selected by the current instruction on the rising edge of tck. shift-dr, exit1-dr, pause-dr, exit2-dr and update-dr these controller states are similar to the shift-ir, exit1-ir, pause-ir, exit2-ir and update-ir states in the instruction path. test-logic reset run-test/ idle 1 0 0 select- dr-scan select- ir-scan 1 1 1 capture-ir 0 capture-dr 0 0 exit1-dr 1 pause-dr 0 exit2-dr 1 update-dr 1 exit1-ir 1 exit2-ir 1 update-ir 1 1 0 1 1 1 6159 drw16 0 shift-dr 0 0 0 shift-ir 0 0 pause-ir 0 1 input is tms 0 0 1 notes: 1. five consecutive tck cycles with tms = 1 will reset the tap. 2. tap controller automatically resets upon power-up. 3. tap controller must be reset before normal queue operations can begin.
32 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 the instruction register the instruction register (ir) is eight bits long and tells the device what instruction is to be executed. information contained in the instruction includes the mode of operation (either normal mode, in which the device performs its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation to be performed, which of the four data registers is to be selected for inclusion in the scan path during data-register scans, and the source of data to be captured into the selected data register during capture-dr. test data register the test data register contains three test data registers: the bypass, the boundary scan register and device id register. these registers are connected in parallel between a common serial input and a common serial data output. the following sections provide a brief description of each element. for a complete description, refer to the ieee standard test access port specification (ieee std. 1149.1-1990). test bypass register the register is used to allow test data to flow through the device from tdi to tdo. it contains a single stage shift register for a minimum length in the serial path. when the bypass register is selected by an instruction, the shift register stage is set to a logic zero on the rising edge of tclk when the tap controller is in the capture-dr state. the operation of the bypass register should not have any effect on the operation of the device in response to the bypass instruction. the boundary-scan register the boundary-scan register (bsr) is 48 bits long. it contains one boundary-scan cell (bsc) for each normal-function input pin and one bsc for each normal-function i/o pin (one single cell for both input data and output data). the bsr is used 1) to store test data that is to be applied externally to the device output pins, and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device input pins. the device identification register the device identification register is a read only 32-bit register used to specify the manufacturer, part number and version of the device to be determined through the tap in response to the idcode instruction. idt jedec id number is 0xb3. this translates to 0x33 when the parity is dropped in the 11-bit manufacturer id field. for the IDT72T51248/72t51258/72t51268, the part number field con- tains the following values: IDT72T51248/258/268 jtag device identification register 31(msb) 28 27 12 11 1 0(lsb) version (4 bits) part number (16-bit) manufacturer id (11-bit) 0000 0033 (hex) 1 jtag instruction register the instruction register allows an instruction to be serially input into the device when the tap controller is in the shift-ir state. the instruction is decoded to perform the following: ? select test data registers that may operate while the instruction is current. the other test data registers should not interfere with chip operation and the selected data register. ? define the serial test data register path that is used to shift data between tdi and tdo during data register scanning. the instruction register is a 4 bit field (i.e. ir3, ir2, ir1, ir0) to decode 16 different possible instructions. instructions are decoded as follows. hex instruction function value 0000 extest test external pins 0001 sample/preload select boundary scan register 0002 idcode selects chip identification register 0003 clamp fix the output chains to scan chain values 0004 high-impedance puts all outputs in high-impedance state 0007 offset read read pae / paf offset register values 0008 offset write write pae / paf offset register values 000f bypass select bypass register private several combinations are private (for idt internal use). do not use codes other than those identified above. jtag instruction register decoding the following sections provide a brief description of each instruction. for a complete description refer to the ieee standard test access port specification (ieee std. 1149.1-1990). extest the required extest instruction places the device into an external boundary-test mode and selects the boundary-scan register to be connected between tdi and tdo. during this instruction, the boundary-scan register is accessed to drive test data off-chip via the boundary outputs and receive test data off-chip via the boundary inputs. as such, the extest instruction is the workhorse of ieee. std 1149.1, providing for probe-less testing of solder-joint opens/shorts and of logic cluster function. sample/preload the required sample/preload instruction allows the device to remain in a normal functional mode and selects the boundary-scan register to be connected between tdi and tdo. during this instruction, the boundary-scan register can be accessed via a data scan operation, to take a sample of the functional data entering and leaving the device. this instruction is also used to preload test data into the boundary-scan register before loading an extest instruction. idcode the optional idcode instruction allows the device to remain in its functional mode and selects the optional device identification register to be connected between tdi and tdo. the device identification register is a 32-bit shift register containing information regarding the device manufacturer, device type, and version code. accessing the device identification register does not interfere with the operation of the device. also, access to the device identification register should be immediately available, via a tap data-scan operation, after power- up of the device or after the tap has been reset using the optional trst pin or by otherwise moving to the test-logic-reset state. device part# field IDT72T51248 04c1 (hex) idt72t51258 04c2 (hex) idt72t51268 04c3 (hex)
33 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 clamp the optional clamp instruction sets the outputs of an device to logic levels determined by the contents of the boundary-scan register and selects the one- bit bypass register to be connected between tdi and tdo. before loading this instruction, the contents of the boundary-scan register can be preset with the sample/preload instruction. during this instruction, data can be shifted through the bypass register from tdi to tdo without affecting the condition of the outputs. high-impedance the optional high-impedance instruction sets all outputs (including two-state as well as three-state types) of an device to a disabled (high-impedance) state and selects the one-bit bypass register to be connected between tdi and tdo. during this instruction, data can be shifted through the bypass register from tdi to tdo without affecting the condition of the device outputs. offset read this instruction is an alternative to serial reading the offset registers for the pae / paf flags. when reading the offset registers through this instruction, the dedicated serial programming signals must be disabled. offset write this instruction is an alternative to serial programming the offset registers for the pae / paf flags. when writing the offset registers through this instruction, the dedicated serial programming signals must be disabled. bypass the required bypass instruction allows the device to remain in a normal functional mode and selects the one-bit bypass register to be connected between tdi and tdo. the bypass instruction allows serial data to be transferred through the ic from tdi to tdo without affecting the operation of the device.
34 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 ef / or (8) 0/1/2/3 t rsf if fwft = high, or = high if fwft = low, ef = low t rsf paf (8) 0/1/2/3 t rsf t rsf q[39:0] t rsf oe = high oe = low 6159 drw17 ow[1:0] (4) , iw[1:0] (4) fsel[1:0] (4) pfm (4) high = synchronous pae / paf timing low = asynchronous pae / paf timing high = fwft mode low = idt standard mode rddr (4) , wddr (4) fwft/si (4) iosel (4) high = read/write double data rate low = read/write single data rate high = hstl i/os low = lvttl i/os t rss t rss t rss t rss t rss t rss if fwft = low, ff = high if fwft = high, ir = low ff / ir (8) 0/1/2/3 pae (8) 0/1/2/3 is[1:0] (4) , os[1:0] (4) t rss t rs mrs wen ren (7) t rss swen , sren t rss t rsr t rsr figure 10. master reset timing notes: 1. oe can toggle during master reset. during master reset, the high-impedance control of the qn data outputs is provided by oe only. 2. prs should be high during a mrs . 3. rclk, wclk and sclk can be free running or idle. 4. the state of these pins are latched when the master reset pulse is low. 5. jtag clock should not toggle during master reset. 6. rcs and wcs can be high or low until the first rising edge of rclk after master reset is complete. 7. eren wave form is identical to ren , erclk wave form is identical to rclk. 8. composite flag wave form is identical to ef , ff , pae , paf wave form above.
35 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 wen , ren t rss prs 2/3 (1) t rss t rsr rclk 123 prs 0/1 (1,3) t rs 4 6159 drw18 ff / ir 0/1 t rsf current state current state ff / ir 2/3 t rsf if fwft = high, ff = high if fwft = low, ir = low if fwft = high, cff = high if fwft = low, cir = low pae 0/1 t rsf current state pae 2/3 t rsf paf 0/1 t rsf current state paf 2/3 t rsf q[39-0] (2,4) t rsf oe = high oe = low current state current state os[1:0], is[1:0] t ens 00 = queue 0 01 = queue 1 ef / or 0/1 t rsf current state current state ef / or 2/3 t rsf if fwft = high, or = high if fwft = low, ef = low if fwft = high, or = high if fwft = low, ef = low cef / cor t rsf current state if fwft = high, cor = high if fwft = low, cef = low output data queue 0 output data queue 1 t rs figure 11. partial reset timing notes: 1. during the input and/or output selection of two queues, partial reset of the two queues involved are prohibited. 2. during partial reset the high-impedance control of the output is provided by oe only. 3. prs 0/1 must go low after the fourth rising edge of rclk/wclk from where is[1:0] and/or os[1:0] transitioned. 4. this is the output data from queue0 and queue1.
36 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 figure 12. write cycle and full flag timing (idt standard mode, sdr to sdr, x40 in to x40 out) wen d[39:0] w d-1 wclk no write ff 0 t wff t dh t ds w d os[1:0] 00=queue 0 t a 6157 drw19 rclk ren 01=queue 1 q[39:0] (4) previous word queue 0 t a t a word 0 queue 2 t a word 1 queue 2 t a t enh t wff t ens t dh t skew1 (3) t ens t enh 10=queue 2 word 2 queue 2 q0 q0 q0 q1 q2 q3 q4 previous word + 1 queue 0 word 0 queue 1 notes: 1. wcs = low, oe = low, wddr = low, rddr = low, and is[1:0] = 00. 2. wclk must be free running for ff 0 to update. 3. t skew1 , is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff 0 will go high (after one wclk cycle plus t wff ). if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then the ff 0 deassertion may be delayed one extra wclk cycle. (see table 6 - t skew measurement). 4. two stage pipeline causes a two-cycle latency on wrtie operations.
37 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 figure 13. write cycle and full flag timing in ddr mode ( idt standard mode, ddr to ddr, x40 in to x40 out) notes: 1. t skew2 is the minimum time between a falling rclk edge and a rising wclk edge to guarantee that ff 0 will go high (after one wclk cycle plus t wff ). if the time between the falling edge of the rclk and the rising edge of wclk is less than t skew2 , then ff 0 deassertion may be delayed one extra wclk cycle. (see table 6 - t skew measurement). 2. oe 0 = low, wcs = low, rcs = low, wddr = high, rddr = high, is[1:0] = 00, and os[1:0] = 00. 3. wclk must be free running for ff 0 to update. word 1 q[39:0] 6159 drw20 t a 12 no write d[39:0] rclk wclk wen ff 0 t clkl t clkh t clk t skew2 (1) 12 t skew2 (1) ren no write w d t ds t ds t dh w d +1 t dh w d +2 w d +3 t wff t wff t wff t wff t enh t ens t enh t ens t a data in output register word 2 word 3 t a t a word 4
38 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 figure 14. write cycle and full flag timing with bus-matching and rate matching (idt standard mode, ddr to sdr, x10 in to x20 out) wclk ff 0 wen rcs t ens t skew1 (1) q[39:0] rclk t enh t ens 1 2 t wff d[39:0] ren t rcslz t a t ds t ds t dh t dh t wff t skew1 (1) t ens t enh t a 1 2 t wff t ds t ds t dh t dh t clk t clkh t clkl no write no write t wff w y w y + 1 wx wx+1 wx+2 wx+3 6159 drw21 notes: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff 0 will go high (after one wclk cycle plus t wff ). if the time between the rising edge of the rclk and the rising edge of the wclk is less than t skew1 , then the ff 0 deassertion may be delayed one extra wclk cycle. (see table 6 - t skew measurement). 2. oe 0 = low, wcs = low, wddr = high, rddr = low, is[1:0] = 00, and os[1:0] = 00. 3. wclk must be free running for ff 0 to update. 4. w x is a 10 bit word. d[39:10] are not used and should be corrected to gnd. 5. w y is a 20 bit word. q[39:20] are not used and should be left open.
39 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 figure 15. write cycle and full flag timing with rate matching (idt standard mode, sdr to ddr, x40 in to x40 out) wclk ff 0 wen rcs t ens q[39:0] rclk t enh t ens 1 2 t wff d[39:0] ren t rcslz t a t ds t dh t ens t enh t a 1 2 t ds t ds t dh t dh t clk no write no write t wff word 1 word 3 w d w d +2 w d +3 t a t ds t dh w d +1 t clkh t clkh t wff t a t skew2 (1) t wff t ens t rcshz word 0 word 2 6159 drw22 t skew2 (1) notes: 1. t skew2 is the minimum time between a falling rclk edge and a rising wclk edge to guarantee that ff 0 will go high (after one wclk cycle plus t wff ). if the time between the falling edge of the rclk and the rising edge of wclk is less than t skew2 , then ff 0 deassertion may be delayed one extra wclk cycle. (see table 6 - t skew measurement). 2. oe 0 = low, wcs = low, rcs = low, wddr = low, rddr = high, is[1:0] = 00, and os[1:0] = 00. 3. wclk must be free running for ff0 to update.
40 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 rclk t skew1 word 0 q[39:0] 6159 drw23 t a previous data in output register t a word 1 t a word 2 word 3 ren t ens or 0 t ref d[39:0] wen wclk t ens word 1 t dh t ds word 0 t enh word 2 word 3 12 3 t dh t a t ref figure 16. write timing in fwft mode (fwft mode, sdr to sdr, x40 in to x40 out) notes: 1. t skew , is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff 0 will go high (after one wclk cycle plus t wff ). if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then the ff 0 deassertion may be delayed one extra wclk cycle. (see table 6 - t skew measurement). 2. wcs = low, oe = low, wddr = low, rddr = low, is[1:0] = 00, os[1:0] = 0, and rcs = low. 3. wclk must be free running for ff 0 to update.
41 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 figure 17. write cycle and first word latency timing in ddr mode (fwft mode, ddr to ddr, x40 in to x40 out) notes: 1. t skew2 is the minimum time between a falling wclk edge and a rising rclk edge to guarantee that or 0 will go low after two rclk cycle plus t ref . if the time between the falling edge of wclk and the rising edge of rclk is less than t skew2 , then or 0 assertion may be delayed one extra rclk cycle. (see table 6 - t skew measurement). 2. oe = low, rcs = low, wcs = low, wddr = high, rddr = high, is[1:0] = 00, and os[1:0] = 00. 3. first data word latency = t skew2 + rclk full period + t ref. 4. rclk must be free running for or 0 to update. wclk wen or 0 t skew2 (1) q[39:0] rclk d[39:0] ren previous data in output register 6159 drw24 t ds t dh word 1 word 2 t enh 12 3 t ds t dh t ds t dh word 3 word 4 t enh t ds t dh t ens t ens t ref t ref t enh t ens t a t a word 1 word 2 t a t a word 3 word 4 t skew2
42 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 rclk ren 12 ef 0 t ref t ref t ref wen d[39:0] q[39:0] t a no read no read t a w d+1 wclk t enh t dh w d+1 6159 drw25 t a t ds t ens t ens t skew t enh t ens w d w d-1 w d-2 figure 18. read cycle, empty flag and first word latency (idt standard mode, sdr to sdr, x40 in to x40 out) notes: 1. oe = low, rcs = low, wcs = low, wddr = low, rddr = low, is[1:0] = 00, and os[1:0] = 00. 2. first data word latency = t skew1 + rclk full period + t ref. 3. rclk must be free running for ef 0 to update.
43 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 ef 0 q[39:0] wclk wen d[39:0] word 0 t ds ren rclk t skew2 12 t ref 6159 drw26 t a word 0 t ens t ens t ens t a t a t a word 1 word 2 word 3 t ref t dh word 1 t ds t dh word 2 t ds t dh word 3 t ds t dh figure 19. read cycle, empty flag and first word latency in ddr mode (idt standard mode, ddr to ddr, x40 in to x40 out) notes: 1. t skew2 is the minimum time between a falling rclk edge and a rising wclk edge to guarantee that ff 0 will go high (after one wclk cycle plus t wff ). if the time between the falling edge of the rclk and the rising edge of wclk is less than t skew2 , then ff 0 deassertion may be delayed one extra wclk cycle. (see table 6 - t skew measurement). 2. oe 0 = low, wcs = low, rcs = low, wddr = high, rddr = high, is[1:0] = 00, and os[1:0] = 00. 3. first data word latency = t skew2 + rclk full period + t ref. 4. rclk must be free running for ef 0 to update.
44 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 q[39:0] (5) wclk wen d[39:0] 6159 drw27 word 0 t ds t dh t enh t ens ef 0 t ref ren rclk t skew2 12 previous data in output register t a word 0 (lsb) t a t ens t ref t a t a no read word 0 (msb) word 1 (lsb) word 1 (msb) word 1 t ds t dh figure 20. read cycle, empty flag and first word latency with bus-matching and rate-matching (idt standard mode, ddr to sdr, x4 0 in to x20 out) notes: 1. t skew2 is the minimum time between a falling rclk edge and a rising wclk edge to guarantee that ff 0 will go high (after one wclk cycle plus t wff ). if the time between the falling edge of the rclk and the rising edge of wclk is less than t skew2 , then ff 0 deassertion may be delayed one extra wclk cycle. (see table 6 - t skew measurement). 2. oe = low, wcs = low, rcs = low, wddr = high, rddr = high, iw = 10, ow = 01, is[1:0] = 00, and os[1:0] = 00. 3. first data word latency = t skew2 + rclk full period + t ref. 4. rclk must be free running for ef 0 to update. 5. word x lsb = d[19:0], word x msb = d[39:20], q[39:20] will be high-impedanced. 6. q[39:20] are not used and must be left open.
45 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 figure 21. read cycle and empty flag timing with bus-matching and rate-matching (idt standard mode, sdr to ddr, x10 in to x20 out) notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef 0 will go high (after one rclk cycle plus t ref ). if the time between the rising edge of wclk and the rising edge of rclk is less than t skew1 , then ef 0 deassertion may be delayed one extra rclk cycle. (see table 6 - t skew measurement). 2. oe 0 = low, rcs = low, wcs = low, wddr = low, rddr = high, iw = 00, and ow = 01. 3. first data word latency = t skew1 + rclk full period + t ref . 4. rclk must be free running for ef 0 to update. 5. word wx lsb = d[9:0], word wx msb = d[19:10]. 6. d[39:10] are not used and should be tied to gnd. q[39:20] are not used and must be left open. q[39:0] t skew1 (1) wclk rclk ren 12 wen t ref ef 0 d[39:0] 6159 drw28 t ref t ref last word (lsb) last 20-bit word (msb) t ens t enh w 0 (lsb) w 0 (msb) w 1 (lsb) t enh t ens w 0 (msb,lsb) t a t a t a t a t ds t dh t ds t dh t ds t dh t dh t ds t clk t clkh t clkl previous data t enh no read w 1 (msb) w 1 (msb,lsb)
46 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 6159 drw29 t a word 0 t a t ens t a rclk q[39:0] ren ir 0 t wff t wff t skew1 12 d[39:0] wen wclk word d+1 t enh t ens t dh t ds word 1 word 2 word 3 figure 22. read timing at full boundary (fwft mode, sdr to sdr, x40 in to x40 out) notes: 1. t skew1 , is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ir 0 will go high (after one wclk cycle plus t wff ). if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then the ir 0 deassertion may be delayed one extra wclk cycle. (see table 6 - t skew measurement). 2. wclk must be free running for ir 0 to update. 3. oe = low, rcs = low, wcs = low, wddr = low, rddr = low, iw = 10, and ow = 10.
47 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 ren ef 1 rclk t a 6159 drw30 12 3 q[39:0] word d-1 queue 1 os[1:0] 01 = queue 1 word d queue 1 t ens t a word a queue 3 t ref cef t ref t ref no read t ds 11 = queue 3 queue 1 status queue 3 status figure 23. composite empty flag (idt standard mode, sdr to sdr, x40 in to x40 out) notes: 1. rcs = low, and oe = low. 2. ef 3 is high. 3. word d-1 is the second to last word in queue 1. word d is the last word in queue 1. 4. word a is the next available word in queue 3. 5. the composite empty flag will update to the newly selected queue after one rclk cycle once a new queue has been selected usin g os[1:0]. ren or 1 rclk t a 6159 drw31 12 3 q[39:0] word d-1 queue 1 os[1:0] 01 = queue 1 11 = queue 3 word d queue 1 t ens t ens t a word a queue 3 t ref cor t ref t ref queue 1 status queue 3 status figure 24. composite output ready flag (fwft mode, sdr to sdr, x40 in to x40 out) notes: 1. rcs = low, and oe = low. 2. or 3 is low. 3. word d-1 is the second to last word in queue 1. word d is the last word in queue 1. 4. word a is the next available word in queue 3. 5. the composite output ready flag will update to the newly selected queue after two rclk cycles once a new queue has been selec ted using os[1:0].
48 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 wen wclk 6159 drw32 cff t wff t wff 12 3 is[1:0] 01 = queue 1 t ens no write d[39:0] word d queue 1 t ds t dh t dh word a queue 3 word a+1 queue 3 ff 1 t wff t ds t dh t ds 11 = queue 3 queue 1 status queue 3 status figure 25. composite full flag (idt standard mode, sdr to sdr, x40 in to x40 out) notes: 1. wcs = low. 2. ff 3 is high. 3. word d is the last word written that causes queue 1 to be full. 4. word a is the next word written to queue 3. 5. the composite full flag will update to the newly selected queue after one wclk cycle once a new queue has been selected using is[1:0]. wen wclk 6159 drw33 cir t wff 12 3 is[1:0] t ens no write d[39:0] t dh ir 1 t wff word d+1 queue 1 t ds t dh word a queue 3 word a+1 queue 3 01 = queue 1 t ds t dh t ds 11 = queue 3 t wff queue 1 status queue 3 status figure 26. composite input ready flag (fwft mode, sdr to sdr, x40 in to x40 out) notes: 1. wcs = low. 2. ir 3 = low. 3. word d+1 is the last word written that causes queue 1 to be full. word d fell through to the output. 4. word a is the next word written to queue 3. 5. the composite full flag will update to the newly selected queue after one wclk cycle once a new queue has been selected using is[1:0].
49 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 figure 27. queue switch at every clock cycle (idt standard mode, sdr to sdr, x40 in to x40 out) notes: 1. the reading and writing to different queues can occur at every clock cycle. there is a two cycle latency pipeline when switch ing from one queue to another. 2. word group a is written into queue 0. word group b queue 1. word group c queue 2. word group d queue 3. 3. the composite empty and full flags will update the status of the newly selected queue one cycle clock after the queue has bee n selected. 4. oe = low, wddr = high, and rddr = high. 5. if fwft mode is selected, the composite input ready flag ( cir ) timing is the same as cef . the composite output ready ( cor ) will update after two clock cycles instead of one. t a is[1:0] wclk wen t ens 00 = queue 0 01 = queue 1 10 = queue 2 11 00 d[39:0] word x queue x word x queue x cff queue x status t ens 00 = queue 0 01 = queue 1 10 = queue 2 11 = queue 3 01 10 queue x status queue 0 status queue 1 status queue 2 status queue 3 status os[1:0] rclk ren q[39:0] cef queue 0 t enh t ds t dh t ens t enh t a queue 0 status queue 0 status queue 1 status queue 2 status 01 10 11 00 01 10 queue 3 status queue 1 status queue 2 status queue 0 status queue 2 status queue 3 status queue 0 status queue 1 status t ens word a queue 0 word a+1 queue 0 word b queue 1 word c queue 2 word c+1 queue 2 word d queue 3 word a+2 queue 0 word b+1 queue 1 word x queue x word e queue 0 word f queue 1 word g queue 2 word h queue 3 wordh+1 queue 3 word f+1 queue 1 word g+1 queue 2 123 word x+1 queue x t a t a t a t a t a t a t a 6159 drw34
50 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 6159 drw35 rclk ren t erclk erclk rcs t ens eren t clken t clken t clken ef 0 t ref q[39:0] t olz t a t a t a t a t a w d-1 w d last word w d-2 w d-3 w d-4 t ens t ens t clken figure 28. echo read clock and read enable operation (idt standard mode, sdr to sdr, x40 in to x40 out) notes: 1. the eren output is ?or gated? to rcs and ren and will follow these inputs provided that the queue is not empty. if the queue is empty, eren will go high to indicate that there is no new word available. 2. the eren output is synchronous to rclk. 3. oe = low, wddr = high, rddr = high, is[1:0] = 00, and os[1:0] = 00. 4. the truth table for eren is shown below: rclk ef rcs ren eren 1000 1011 1101 1111 0xx1
51 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 figure 29. echo rclk and echo read enable operation (fwft mode, sdr to sdr, x40 in to x40 out) notes: 1. the o/p register is the internal output register. its contents are available on the qn output bus only when rcs and oe are both active, low, that is the bus is not in high-impedance state. 2. oe is low. cycle: a&b. at this point the queue is empty, or 0 is high. rcs and ren are both disabled, the output bus is high-impedance. c. word wn+1 falls through to the output register, or 0 goes active, low. rcs is high, therefore the qn outputs are high-impedance. eren goes low to indicate that a new word has been placed into the output register. d. eren goes high, no new word has been placed into the output register on this cycle. e. no operation. f. rcs is low on this cycle, therefore the qn outputs go to low-impedance and the contents of the output register (wn+1) are made ava ilable. note: in fwft mode it's important to take rcs active low at least one cycle ahead of ren , this ensures the word (wn+1) currently in the output register is made available for at least one cycle, otherwise wn+1 will not be overwritten by wn+2. g. ren goes active low, this reads out the second word, wn+2. eren goes active low to indicate a new word has been placed into the output register. h. word wn+3 is read out, eren remains active, low indicating a new word has been read out. note: wn+3 is the last word in the queue. i. this is the next enabled read after the last word, wn+3 has been read out. or 0 flag goes high and eren goes high to indicate that there is no new word available. 4. oe = low, wddr = low, rddr = low, is[1:0] = 00, and os[1:0] = 00. 5. the truth table for eren is shown below: q[39:0] o/p (1) reg. t a t ref or 0 6159 drw36 t rcslz ren t ens t enh rcs t ens rclk a b c d e f g h i w n+1 wclk wen d[39:0] t skew1 t ens t ds t enh w n+2 w n+3 erclk eren t clken t clken t clken t clken w n+1 w n+2 w n+3 t a t ref w n+1 w n+2 w n+3 w n last word t dh t dh t dh t ds t ds 1 2 t erclk high-z t enh rclk or rcs ren eren 0000 0011 0101 0111 1xx1
52 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 figure 30. echo read clock and read enable operation (idt standard mode, ddr to ddr, x10 in to x10 out) notes: 1. the eren output is ?or gated? to rcs and ren and will follow these inputs provided that the queue is not empty. if the queue is empty, eren will go high to indicate that there is no new word available. 2. the eren output is synchronous to rclk. 3. oe = low, wddr = high, rddr = high, is[1:0] = 00, and os[1:0] = 00. 4. the truth table for eren is shown below: eren ef 0 t ref q[39:0] t clken t clken t olz t a t a t clken t a t olz t olz t a t a t a t a t a w d-10 w d-9 w d-8 w d-6 w d-5 w d-4 w d-3 w d-2 last word w d 6159 drw37 t a w d-7 w d-6 t a w d-1 rclk ren erclk rcs t ens t erclk t enh t ens t enh t clken t clken t clken t ens no read no read t ens rclk ef rcs ren eren 1000 1011 1101 1111 0xx1
53 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 figure 31. loading of programmable flag registers (idt standard and fwft modes) t senh t sdh sclk swen fwft/si 6159 drw38 empty offset 3 full offset 3 t sens t sds bit x (1) 8 bit 1 t scl k t sckh t sckl bit 1 (lsb) empty offset 0 full offset 0 bit 1 bit 1 (lsb) bit x (1) 8 bit x (1) 8 bit x (1) 8 (msb) (msb) figure 32. reading of programmable flag registers (idt standard and fwft modes) sclk sren sdo 6159 drw39 empty offset 3 full offset 3 t sens t soa t sen h bit x (1) t senh t sclk t sckh t sckl bit 0 bit 0 bit x (1) bit x (1) t soa bit 0 empty offset 0 full offset 0 bit 0 (lsb) bit x (1) (msb) (lsb) (msb) note: 1. if iw/ow = x40, x = 104 for the IDT72T51248, x = 112 for the idt72t51258, x = 120 for the idt72t51268. if iw/ow = x20, x = 112 for the IDT72T51248, x = 120 for the idt72t51258, x = 128 for the idt72t51268. if iw/ow = x10, x = 120 for the IDT72T51248, x = 128 for the idt72t51258, x = 136 for the idt72t51268. note: 1. if iw/ow = x40, x = 104 for the IDT72T51248, x = 112 for the idt72t51258, x = 120 for the idt72t51268. if iw/ow = x20, x = 112 for the IDT72T51248, x = 120 for the idt72t51258, x = 128 for the idt72t51268. if iw/ow = x10, x = 120 for the IDT72T51248, x = 128 for the idt72t51258, x = 136 for the idt72t51268.
54 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 wclk wen paf 0 rclk ren 6159 drw40 1 2 12 d - m0 words in queue (1) d - (m0 +1) words in queue (1) t enh t ens t pafs t ens t enh t clkl t skew2 (3) t pafs t clkl wclk wen pae 0 rclk 12 12 ren 6159 drw41 n0 words in queue t ens t skew2 (4) t enh t paes n0 + 1 words in queue (2) , n0 + 2 words in queue (3) t ens t enh t clkh t clkl notes: 1. m0 = paf 0 offset . 2. d = maximum queue depth. for density of queue with bus-matching, refer to the bus-matching section pages 17-20. 3. t skew2 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that paf 0 will go high (after one wclk cycle plus t pafs ). if the time between the rising edge of rclk and the rising edge of wclk is less than t skew2 , then the paf 0 deassertion time may be delayed one extra wclk cycle. 4. paf 0 is asserted and updated on the rising edge of wclk only. 5. rcs = low, wcs = low, wddr = low, rddr = low, is[1:0] = 00, and os[1:0] = 00. figure 33. synchronous programmable almost-full flag timing (idt standard and fwft mode, sdr to sdr, x40 in to x40 out) notes: 1. n0 = pae 0 offset. 2. for idt standard mode 3. for fwft mode. 4. t skew2 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that pae will go high (after one rclk cycle plus t paes ). if the time between the rising edge of wclk and the rising edge of rclk is less than t skew2 , then the pae 0 deassertion may be delayed one extra rclk cycle. 5. pae 0 is asserted and updated on the rising edge of wclk only. 6. rcs = low, wcs = low, wddr = low, rddr = low, is[1:0] = 00, and os[1:0] = 00. figure 34. synchronous programmable almost-empty flag timing (idt standard and fwft mode, sdr to sdr, x40 in to x40 out)
55 commercial and industrial temperature ranges IDT72T51248/72t51258/72t51268 2.5v multi-queue ddr flow-control devices 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4 figure 35. power down operation 6159 drw44 wclk wen d[39:0] t ds t dh t dh w d10 w d11 t ds t dh t ds w d13 rclk ren t a t a t a t erclk t pdhz (7) t pdlz (2) t pdl t pdh (2) t pdh (2) w dh (8) hi-z hi-z w d4 w d3 w d2 w d1 hi-z t eren q[39:0] pd erclk eren 12 3 4 (1) t ds 1 s t a t eren w ds w d12 notes: 1. all read and write operations must have ceased a minimum of 4 wclk and 4 rclk cycles before power down is asserted. 2. when the pd input becomes deasserted, there will be a 1 s waiting period before read and write operations can resume. all input and output signals will also resume after this time period. 3. set-up and configuration static inputs are not affected during power down. 4. serial programming and jtag programming port are inactive during power down. 5. rcs = 0, wcs = 0 and oe = 0. these signals can toggle during and after power down. 6. all flags remain active and maintain their current states. 7. during power down, all outputs will be in high-impedance. 8. wdh = wd4 before power down.
56 corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 408-330-1533 santa clara, ca 95054 fax: 408-492-8674 email: flow-controlhelp@idt.com www.idt.com plastic ball grid array (pbga, bb324-1) commercial (0 c to +70 c) industrial (-40 c to +85 c) low power 6159drw45 commercial and industrial commercial and industrial idt xxxxx device type x power xx speed x package x process / temperature range blank i (1) 72t51248 8,192 x 40 x 4 ? 2.5v multi-queue ddr flow-control device 72t51258 16,384 x 40 x 4 ? 2.5v multi-queue ddr flow-control device 72t51268 32,768 x 40 x 4 ? 2.5v multi-queue ddr flow-control device clock cycle time (t clk ) speed in nanoseconds bb 5 6-7 l ordering information note: 1. industrial temperature range product for the 5ns and 6-7 speed grades are available as a standard device. datasheet document history 12/01/2003 pgs. 1, 5, 11, and 29.

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